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Recent content by jiesteve

  1. J

    what is value of I1 and I2 ?

    Hi erikl, what tool are you using to generate the dc operation point picture? thanks
  2. J

    How to add notes in CMOS layout?

    In our cadence toolkits we have a layer called "Scratch" where you can type in layout notes.
  3. J

    comparator input->output time limit

    Understand that the speed of the comparator depends on how big your input is (i.e. the precision requirements of the comparator). More precision -> slower
  4. J

    How to simulate the settling time of a DC offset cancellation circuit?

    It's just like simulating the amp with an input signal, except you should feed in your worst case input-referred offset as the input.
  5. J

    [SOLVED] How to calculate the input-referred offset voltage?

    The overall offset is a combination of the input-referred offset of the input pair and PMOS mirror: Vos = Vos(input pair) + Vos(pmos mirror) = Avtn / sqrt(Wn*Ln) + gmp*(Avtn/sqrt(Wp*Lp) / gmn gmp*(Avtn/sqrt(Wp*Lp) is the current mismatch (gm*delta_vth) of the PMOS mirror, dividing by the...
  6. J

    18% layout mismatch of a current mirror

    Re: layout mismatch? Probe the voltages -- there could be some mismatch between diode and mirror legs. Also ensure that cascodes are in saturation
  7. J

    Reducing kickback noise

    I have a regular single stage diffamp in unity gain configuration buffering a VREF signal. Whenever the diffamp powers on or off, it kicks back noise onto the VREF line... What are some (clever) ways to minimize/reduce this kickback noise? Thanks in advance.
  8. J

    A design problem regarding voltage generator

    Re: A design problem The circuit above requires a negative rail. I only have VSS=0... How do I get around that? Wouldn't the op-amp just rail to 0 ?
  9. J

    A design problem regarding voltage generator

    Re: A design problem Thanks. Could you please show how I can make a PVT independent voltage DAC to generate V2? Also, how can I make Vo positive (remove the negative sign) ? Thanks
  10. J

    A design problem regarding voltage generator

    Let's say I have a voltage generator that generates a voltage called V1. I want to produce an output, Vout where Vout = V1 + V2. I want V2 to be some sort of voltage DAC, that is process and temperature independent. Could you please give some circuit solutions, and the pros/cons of each...
  11. J

    HSPICE Matlab toolbox

    Any ever use the HSPICE matlab toolbox developed by MIT? Anyone know how to make it work with eldo output? It's expecting an HSPICE binary output file... is there a switch in eldo to generate an HSPICE binary output ? thanks!
  12. J

    SPICE testbench for singled-ended output Op Amp

    Can anyone point me to a nice SPICE testbench for a single-ended output Op Amp? Thanks!
  13. J

    Equation to show the relation between Vds(saturation) and W/L

    Re: Vds and W/L Well, the long channel equation for Vdsat is: Vdsat = SQRT( 2 Id / k` (W/L) )
  14. J

    unity gain amplifier output higher than input?

    Thanks everybody. I've convinced myself that it is systematic offset. Thanks!
  15. J

    Regarding 1 rule of RF devices-

    Probably because the extra routing required for common centroid matching adds too much capacitance and kills the bandwidth.
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