Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by jgnr

  1. J

    Unconstrained PAth in a fulladder design - DC

    Thanks again. Adder design: module adder_reg ( input A,B,Cin,clk,rst, output Cout, output reg Sum_reg ); wire Sum; always @(posedge clk or posedge rst) begin if(rst) Sum_reg <= #1 1'b0; else Sum_reg <= #1 Sum; end assign {Cout,Sum} = A + B + Cin; endmodule...
  2. J

    Unconstrained PAth in a fulladder design - DC

    Thanks by your answer. Indeed, that adder design was a litle bit strange. I follow your steps, changed the description and tryed to synthesize it again. But the path continues unconstrained. It generates the mapped circuit as before. What disgust me is that I had synthesized some FIR...
  3. J

    Unconstrained PAth in a fulladder design - DC

    Hello everybody, I'm trying to sinthesize a full combinational design in Design Compiler. But i'm having some problems with paths unconstrained in report_timing. Let's start... Here is an example of .sv code that i'm using to define a fulladder: module fulladder(clk, CIN, A, B, COUT, S)...
  4. J

    LCD Display Code using VHDL

    Hello, I'm having the same problem.... I'm trying to change de word shown in the displays but everything i tried didn't work. Could you make it work?
  5. J

    Synopsys Tools - Problems with openSUSE 12.2 32-b

    Hello everybody, I'm doubt about wich files i need to use in installing vcs tool at openSuse12.2 32b. Do I need to install the common.tar and (linux.tar or suse32.tar)? I've installed the suse32.tar but now when I'm executing the vcs in command line the terminal gives this message: # vcs...
  6. J

    Error on readign a .db file!

    So, I tryed to use de comand write -format ddc -hierarchy -output $active_design.db It generated the .db files but this files were not read by the tool as before. I tryed to use de command: write -format db -hierarchy -output $active_design.db But the tool returns this error: Error...
  7. J

    Error on readign a .db file!

    Thanks yang, both steps help me, but now the tools return this message: Error: File is not a DB file. (DB-1) Error: The file '/home/joaonizer/filtros/slogica/018/teste/work/DB_SV/fulladder.db' is not a DB file. No designs were read But this files were generated by the own tool when i...
  8. J

    Error on readign a .db file!

    The .db file are located inside of the directory DB_SV. I added it on the search_path before i post here, and error occurred already. Some help? Thanks oratie.
  9. J

    Error on readign a .db file!

    Sorry about my late for answering. I tryed put the .db file in the same directory that i invoke dc_shell but the same error occurred. I'll put the code i'm using on .synopsys_dc.setup: set search_path [list ../../XFAB018 ../RTL /DB_SV] set target_library [list...
  10. J

    Error on readign a .db file!

    Hello folks, I'm using the book "Advanced-ASIC-Chip-Synthesis-Using-Synopsys-Design-Compiler-Physical-Compiler-and-Primetime-2nd-E" and i'm trying to do the logical synthesis of some block wich uses other sub-blocks. So, first of all i'm using a script to synthesize the sub-block that works...
  11. J

    Error using Design Compiler

    I tried, but didn't work. I found a way to the synthesis works, let me explain what did i do: Remove de command <set hdlin_auto_save_templates "true"> from .scr (i read in somewhere that this setting would not be used in DC version after 2007); Change the way to read de .sv files from <analyze...
  12. J

    Error using Design Compiler

    So, a friend mine made a synthesis for a floating point unit 32 bits single precision on it. Using SV. But the code generated by the tool, with the mapped code, it is in verilog. But he is not an undergraduate student anymore, and it is a little complicated to talk with him, so i'm using the...
  13. J

    Error using Design Compiler

    As you suggested, i tried to synthesis two different designs, actually, i used some designs that were instantiated in the main design who are giving the error. Both, 32-bits adder and Latch D, didn't give the error. The tool works fine, and give me all the reports, area, timing and power. I...
  14. J

    Error using Design Compiler

    Hello everyone, I'm using dc_shell to the logical sinthesis and when the tool began the mapping optimization sometimes occurres this error: Beginning Mapping Optimizations (Medium effort) ------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN...
  15. J

    question about primetime PX: about using create_power_waveforms

    I'm having the same problem Zoyoung, i'm geting to run the power analasys, but i'm with this warning too. The code that i'm using to run is: #power.scr set power_enable_analysis TRUE set power_ui_backward_compatibility TRUE set target_library "<yourlibrary>.db" set link_library...
See more

Part and Inventory Search

Back
Top