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Recent content by jesseyu1984918

  1. J

    Will stand-alone LDO contain capacitor on its chip?

    Hi, I'm quite intrested fo learn if those stand-alone LDO has its own on-chip capacitor? Since for an LDO chip, it has quite big area( say 3mm by 3mm on a datasheet), wouldn't it be good to use those space to build capacitor on chip? maybe it will save the cap outside. But this also will...
  2. J

    temprature stability of bandgap design

    The TC alone doesn't affect your final TC since it's Vbe +deltaVbe, even though the TC for BJT is big, it doesn't necessarily means the bandgap can't be designed, usually the accuracy is mainly affected by 3-sigma variation of the device rather than the TC of the device.
  3. J

    cmos amp design: input is close to ground

    I think you could use PMOS input differential pair and using very small W/L ratio.
  4. J

    Why it is called DC-Gain, while doing AC analysis

    DC means no capacitance and inductance while AC have
  5. J

    Phase Locked Loop - transistor sizing forphasedetector

    Phase Locked Loop Did you apply too fast input to your logic gate? Usually for D-flip flop, you need enough set-up and hold time in order to make it latch the input, I think you could check on this.
  6. J

    How to compensate super source follower?

    super source follower Hi, I'm doing a project now using super source follower, besides itself is a negtive feedback system, it is also in a bigger loop( you can find this paper naming"A transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation"), it...
  7. J

    How to compensate a super source follower?

    explain super source follower Hi, I'm doing a project now using super source follower, besides itself is a negtive feedback system, it is also in a bigger loop( you can find this paper naming"A transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance...
  8. J

    Milliken's capless LDO technique

    ldo rf soc thesis Hi, One question about the capless LDO? Does it mean it can work only without cap? I don't think it will be the case since some pass transistors will always be added to enhance the transient repsonse, say spike or dip, in such case, is it possible to develop a LDO that is...
  9. J

    NEED YOUR HELP~want to amplify a signal that is DC value

    Re: NEED YOUR HELP~ This would actually rely on your load, what do you want to drive and what performance do you want?
  10. J

    How to design a sense amplify in SRAM?

    I always see how much supply you can get at first, then decide what will the vdsat be cause the vdsat could be decided by sizing the transistor. usually it is recomended to be 1/10 of the supply voltage, say, 2V, a vdsat of 200mV will turns out to be just balance for performance, however, this...
  11. J

    how to implement flip-flop in integrated circuit

    Just like you will see in the link provided by trekkytekky, very good material
  12. J

    Bandgap output impedance...Pls help...

    should plus a buffer for LDO somthing to reduce it
  13. J

    How to design a sense amplify in SRAM?

    The gain of the circuit is decided by two things, one is Vdsat, the other is the channel length of the circuit. The other thing is the slew rate you want, as how much current you need for the circuit speed.

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