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spectreverilog
Hi there,
I'm a new user to cadence IC6.1 and I have some trouble getting the spectreVerilog simulator running properly. I've been using IC5141 for a long time and I simply followed the same steps in IC5141 to setup the spectreVerilog simulator in IC6.1. Here is my setup:
1...
I'm using xstream to import/export the layout, the process can't be finished with the warning. I think I need to set some "Via Map File" in the "Stream-Out Options" window. Anyone has any idea what that file is?
I've heard that new IC6.x cadence does not have pcells for vias in the technology library. The problem right now is: I can create via in the layout using Create-->Via function, but when I do Calibre DRC or LVS, the vias are not recognized. Is there anything I should setup for the Calibre in...
via map option + cadence
Yes I have created my own library the way you mentioned. In the LSW window I can see all the via layers, but I can't find any via cells from the technology library. I'm wondering if there is anything different in linux cadence from unix cadence, which I have been using...
cmos10lpe
Guys,
I'm currently running Cadence (IC6.1) under linux and I have downloaded this cmos10lpe library from MOSIS. In the technology library I can't find any metal contacts. Does that mean the library is incomplete or the new version of Cadence stores the vias in different manner from...
Thank you guys for replying, I found the timing font quite handy since I can do it directly in word and my timings are not really that complicated, you know, for analog circuits:D:D
For more complicated digital circuits timing I may look into other options you guys suggested, but thanks again...
timing diagrams drawing cadence
For some circuits like switched-capacitor circuit we need to use timing diagram to explain the operation, question is what software you guys use to draw beautiful timing diagram, or you just snapshot the simulation results directly from cadence? Thanks!
failed to build vdb. cannot submit drc run.
Friends,
I'm using IBM cms9flp technology for circuit design. When I tried to do DRC on my layout using Assura-->DRC, an error message popped up, saying "Failed to build VDB, can't submit DRC run". I'm pretty sure the design rule path and switch name...
spice icm7555
Thanks for your reply.
Actually I'm modifying a circuit that may have durability issues and I particularly want to simulate ICM7555 because it's in the circuit. I'm more interested in the performance rather than functionality of the timer. I want to get into really detailed DC and...
icm7555 not working
Friends,
I originally posted this question in Analog Design section, but I think it might be more appropriate to post here.
I'm using protel to do some simulations and in my circuit there is a ICM7555 cmos 555 timer. I downloaded a couple of spice model files for this...
icm7555
Thank you!
I'll definitely try it out.
One question though, since this 555 timer is just one of the modules of a big cirucit, should I attach .ckt file (spice subcircuit) as the model file for the timer? The files I found on the web all have .LIB extension... and the file you presented...
555 timer pspice model
Friends,
I'm looking for spice model of ICM7555 cmos timer because I want to do some board level simulation using protel DXP. Does anybody have it. I downloaded a couple of files from internet but they don't seem to be correct. Thanks!
Jerry
8 bit divider
Hey guys,
I'm currently looking for a good Architecture for 8-bit divider (the divident is 16-bit and divisor is 8-bit, the quotient is supposed to be 8-bit). The one I previously used was some "restoring division algorithm" and 16 iterations of subtractions are needed to obtain...
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