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Thank you FvM and TrickyDicky. I know generic is not needed in my example, but I want to use this in some other designs. That was just an example, not design.
TrickyDicky, I got it. Thanks for suggesting the instance of the package. I am using synplify and will check wether its gonna work there...
I have defined a generic in entity and I want to pass it to package. How to do this, without using component and others. I read somewhere that VHDL-2008 provides this feature. But I don't know how to use it? This is what I am trying to do (just an example):
library ieee;
use...
I was doing digital design with Verilog using Xilinx ISE. Now I want to start analog design using Verilog-ams. But I don't know which simulator (freeware) I should use, because Xilinx ISE is not supporting analog designs with Verilog ams. Please suggest me some simulators supported to verilog...
I am getting an error at the udp instantiation line, while viewing RTL schematic, as: Unsupported Switch or User Defined Primitive
but syntex is correct.... help me.. I am using xilinkx 14.1
primitive udp (d,a,b,c);
output d;
input a,b,c;
table
//a b c : d;
0 0 0 : 0;
0 0 1 : 1;
0...
I am getting an error as while designing an OAI22 in verilog(Xilinkx ISE 14.1) : ERROR:HDLCompilers:26 - "OAI21.v" line 26 expecting 'endmodule', found 'if'
21: module OAI21(a, b, cntrl, z);
22: input a, b, cntrl;
23: output z;
24: reg z;
25: always @(a or b or cntrl);
26: if (cntrl)
27: z = a &...
I am getting an error as: ERROR:HDLCompilers:26 - "OAI21.v" line 26 expecting 'endmodule', found 'if'
21: module OAI21(a, b, cntrl, z);
22: input a, b, cntrl;
23: output z;
24: reg z;
25: always @(a or b or cntrl);
26: if (cntrl)
27: z = a & b;
28: else
29: z = a | b;
30: endmodule...
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