jeetesh
Newbie level 4

I have defined a generic in entity and I want to pass it to package. How to do this, without using component and others. I read somewhere that VHDL-2008 provides this feature. But I don't know how to use it? This is what I am trying to do (just an example):
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 library ieee; use ieee.std_logic_1164.all; package pack is generic(N: integer := 15); port ( in1, in2: std_logic_vector(N downto 0)); function and15(in1, in2: std_logic_vector) return std_logic_vector; end pack; package body is function and15(in1, in2: std_logic_vector) return std_logic_vector is variable result: std_logic_vector(N downto 0); begin result := in1 and in2; end pack; library ieee; use ieee.std_logic_all; use work.pack.all; entity andgate is generic(N: integer := 15); port (in1, in2: std_logic_vector(N downto 0); out1: std_logic_vector(N downto 0)); end andgate; architecture arch of andgate is begin out1 <= and15(in1, in2); end arch;
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