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To further reduce input voltage offset,
we shall need calibration / auto-zero-ing techniques
commonly deployed in > 10bit data convertors.
Please check with papers,
Good luck.
cmfb switch
Dear Sir,
May we know how you perform CMFB simulation with ideal switch.
Did you keep feedback / sampling capacitors same as in MOS switch case?
Dear Sir,
Experiment with blue curve is more similar to our real life experience.
Here we assume your RTC want to work at low power region (likely < 10uA)
Meanwhile, resistance of mos switch seems over estimated.
mos switch of 15MEG is rarely found.
We need to know more detail about how you...
Re: Comparator design
With above saying multi-stage, gain of a few thousands is not problem.
Another limiting factor of resolution is offset voltage (matching of input MOS).
We need to use size enough to make offset statistically small enough (say, less than 1mV).
Good Luck,
Re: bandgap reference
Dear crazyfox,
Your circuit seems working, and it's natural that BGR behavior varies with VDD from 2.8V to 5.5V. You can check if DC operating points all shift.
One common solution to this problem is to add LDO on top of BGR unless you would like to try very high PSRR...
Re: Comparator design
Theoretically, yes, if the input stages gets saturated by DC, then the whole mechanism collapse.
In practice, comparator are not totally the same as opamp in that
we often add differential type cross-coupled latch stage before digital output buffer. And even in cases where...
Re: latch-up
Yes sir,
When latch-up, the system goes into steady state with significant amount of current which can be identified under EMMI scope until we remove the VDD.
Have fun,
Re: about comparator design
Haff99 is right.
Bode plot is must for amplifier because they go with feedbacks.
When we use comparator, it goes beyond linear domain.
No feedback needed, hence no stability criterion.
In cases where system gets feeback like in sigma-delta convertors,
that's system...
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