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The substrate is P-type.
p-type analog (-3.3V) ||| n+ guard ring (+3.3V) ||| p-type digital (0V)
-3.3V --->|----- 3.3V -------|<----- 0V
It seems like even if the analog p-sub is connected to 0V and the digital p-type sub is connected to 0V...
Hey all,
I am working on an analog to digital converter. The basic problem I am encountering is that in one portion of my circuit I need to operate on 0-3.3V (digital part) and in another portion (analog part) I need to operate on -3.3V to 3.3V.
Since the NMOS substrates are all tied...
Hey all,
I am working on constructing a simple 8 bit flash ADC to operate from 0-3.3V. I am planning on using a pipelined, recycled architecture (2 2-bit ADC's in a pipelined fashion form 4 bits. These bits are recycled to create 4 more bits). It will be constructed using 2-bit ADC's which...
Hey all,
I am currently working on a Master's Thesis for Electrical Engineering and am very interested in the Delta-Sigma ADC using a VCO. I am having trouble finding a solid starting reference for this topic, however in the meantime I have a few questions about these papers if anyone can...
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