jbord39
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Hey all,
I am working on constructing a simple 8 bit flash ADC to operate from 0-3.3V. I am planning on using a pipelined, recycled architecture (2 2-bit ADC's in a pipelined fashion form 4 bits. These bits are recycled to create 4 more bits). It will be constructed using 2-bit ADC's which are implemented using inverters as comparators (to reduce static power consumption). The inverters Wp/Wn ratio's are varied to form the switching thresholds of the inverters. Here is where my question begins:
The 2-bit ADC's are not linear over the entire range. The switching thresholds are 1V, 1.65V, and 2.3V (ideally they would be .825V, 1.65V, 2.475, but these switching thresholds cannot be reached without ridiculous Wp/Wn ratios due to the logarithmic dependence on Vs). So, really the linear input range seems to be .45V-2.95V.
I am not sure exactly how to tackle the problem. Here is what I have been considering:
1. Somehow compressing the input signal around 1.65V by about 25%.
2. Instead compensating for the nonlinearity when generating the residue through non-linear DAC's.
My Thesis advisor is no help, and while I have decent background in designing analog circuits using BJT's, I am having a hard time innovating in CMOS.
Any advice or references are greatly appreciated.
Thanks for any help,
John
I am working on constructing a simple 8 bit flash ADC to operate from 0-3.3V. I am planning on using a pipelined, recycled architecture (2 2-bit ADC's in a pipelined fashion form 4 bits. These bits are recycled to create 4 more bits). It will be constructed using 2-bit ADC's which are implemented using inverters as comparators (to reduce static power consumption). The inverters Wp/Wn ratio's are varied to form the switching thresholds of the inverters. Here is where my question begins:
The 2-bit ADC's are not linear over the entire range. The switching thresholds are 1V, 1.65V, and 2.3V (ideally they would be .825V, 1.65V, 2.475, but these switching thresholds cannot be reached without ridiculous Wp/Wn ratios due to the logarithmic dependence on Vs). So, really the linear input range seems to be .45V-2.95V.
I am not sure exactly how to tackle the problem. Here is what I have been considering:
1. Somehow compressing the input signal around 1.65V by about 25%.
2. Instead compensating for the nonlinearity when generating the residue through non-linear DAC's.
My Thesis advisor is no help, and while I have decent background in designing analog circuits using BJT's, I am having a hard time innovating in CMOS.
Any advice or references are greatly appreciated.
Thanks for any help,
John