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Combining two ELFs that have an entrypoint defined like main() is not possible. The reason for this is that they were built as independent executables meant to run on their own and aside from main() don't export symbols for further linking, so you'd never be able to resolve functions calls.
I'm...
1) a radio button is a button control with the BS_RADIOBUTTON style applied. To create a group of buttons you need to individually create them and intercept the BN_CLICKED notification in the parent window, you could manually handle the check state of the buttons in the group or you could use...
what is ah/ assembly language
At minimum LEA needs a 16-bit destination register to store the address, DL is an 8-bit register.
STRIP DB DUP(?) is invalid since the syntax for DUP is:
count DUP (initialvalue [[, initialvalue]]...)
assembly language db
Have you tried changing LEA DL,[SI] to MOV DL,[SI]
How is memory for STRIP allocated? Have you considered defining it as:
STRIP DB 00H,00H,00H,00H,00H,00H...
l6236e
Do you only have two source files in your project? startup.s and <hello>.s?
startup.s makes reference to external symbols, after it does the initial setup it branches main, so a function by that name should be in one of the source files.
To resolve the main symbol, create a C file with...
c++ link command
cl.exe is the compiler, by default cl.exe will link unless you explicity choose to only create object files and link later.
link.exe is the linker
atmel sam-ice
The Atmel SAM-ICE is an OEM version of the Segger J-Link and only works with the AT91 series ARM microcontrollers.
Is it possible to convert the Atmel SAM-ICE into a non-restricted Segger J-Link capable of working with other manufacturers ARM microcontrollers?
- Jayson
It can generate an RTL schematic and you can go look at how the design is implemented.
Another tool which maybe of interest is HDL Ease, it can take VHDL and create block diagrams of a design.
- Jayson
vhdl code for t flip flop
Here's a T flip flop with reset
library ieee;
use ieee.std_logic_1164.all
entity tff is
port(
clk: in std_logic;
reset: in std_logic;
t: in std_logic;
q: out std_logic
);
enf tff;
architecture behave of tff is
signal q_reg...
Hi all,
Is there an advantage to writing testbenches in Verilog (i.e. easier, faster?) than in VHDL.
Recently I saw code in VHDL but the testbenches were written in Verilog, is there a reason somebody would write a testbench in Verilog rather than VHDL? Is Verilog better suited for testbenches?
An easy way would be to use the first few terms of the Taylor expansion of sine and/or cosine and use opamps to implement the additions and multiplications.
-Jayson
significance of eigen values
Hi,
Eigen values give you the characteristic equation of a system, in fact when you solve a an RLC circuit using differential equations Aλ^2+Bλ+C=D(λ), the solution to Aλ^2+Bλ+C =0, are the eigen values of the system.. Therefore the geometrical significance of...
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