Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by InverseUniverse

  1. I

    Help!! trying to understand this circuit

    Hi All I am trying to understand what the attached circuit is trying to do but need help with that. Looking at the circuit the first OP AMP on the left is configured as an integrator clearly as there is the capacitor in the feedback path, but I do not understand what the second op-amp is...
  2. I

    JPEG encoding with Huffman code

    Hi All I just wanted to confirm my understanding of the JPEG encoding method using Huffman code: 1. Matrix converted into a 1D sequency with a zigzag pattern. 2. The DC coefficient is encoded with DPCM (DC element of all blocks is relative to the 1st by difference). 3. A header is created...
  3. I

    2D DCT compression with FPGA question

    Hey guys I am working on implementing the algorithm of 2D DCT on Nexy2 from Digilent, which is based on Xilinx Spartan 3E. My main concern is data precision and its implications on the memory. The board has 16MB SDRAM (which I am planning to use for this calculation) and 16MB Flash Memory...
  4. I

    Design of Flash ADC for 6bit

    U Hi devra, Your question is kind of very generic. In general to start your drsign you need a specific technology to work with. Realated to a specific IC foundry. Then you will use these technology files to make your design. Since you have aschematic and a final layout, you need to design...
  5. I

    Design of Flash ADC for 6bit

    Hi Dev, What do you need help with exactly ?
  6. I

    pdk for IBM 8RF-DM CMOS Process - Ledit

    Hi, Foundries like Tower and OnSemi provide already made PDKs in Tanner format
  7. I

    capcitance value after extraction .?

    Hi, There is a problem with that capacitor's extraction as you are supposed to see other parameters there. you need to look at the device extraction rule set and see if the device is generated accordingly
  8. I

    Conversion of schematic to layout in Tanner EDA15

    Hi somulu! You use S-EDIT for your schematic, LEDIT is for the layout. To transfer your schematic to a layout, you need to use SDL. just go to File>Export>SPICE In the SPICE dialog, you'll see a list at the bottom, type "SDL". then export your SDL SPICE netlist that resulted by clicking OK...
  9. I

    need help with tanner eda licensing error LSERVRC not found

    Hi mansi0905 you need to make sure you double clicked the .tlu file and installed it, if you are using a server machine, do this on your server machine and not the user one all the best!
  10. I

    Need an extract definition file (.ext) for TSMC 0.18u-Help !

    Hi You could obtain the Calibre files by contacting Tanner support and providing a NDA (non-disclosure agreement) that you obtained from the foundry. http://www.tannereda.com/
  11. I

    [Tanner EDA - UPI] - Configuring SPR settings using UPI.

    Hi there! have you tried contacting them thru their support page? http://www.tannereda.com/
  12. I

    cadence vs tanner L-edit

    Hi, MOSIS does provide libraries in Tanner format. Take a look at their website: http://www.tannereda.com/foundries You can also contact them and ask from the support
See more

Part and Inventory Search

Back
Top