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Recent content by imfresh

  1. I

    how to simulate PSRR of VCO

    Thanks for your reply. I added a sin wave to power supply, and then run tran simulation, finally check the output frequency. And I calculate psr of VCO = delta(fout)/delta(vdd). Is this method right?
  2. I

    how to simulate PSRR of VCO

    Hi, all plz help me, I want to know how to simulate psrr of vco.(spectre) Is it possible to use ac simulation for psrr? Or tran? Or others? Thanks
  3. I

    how to increase the frequency of current steering DAC?

    Thank you for your reply. settling time is limiting me. and LSB current is fixed too.
  4. I

    how to increase the frequency of current steering DAC?

    Hi, all The DAC's load res and cap are fixed, so how to increase the frequency of this DAC? thanks
  5. I

    question about noise_table function in veriloga

    Hi, all I am using noise_table function, but I don't konw how to use it. for example: I have -60dbc/hz at 10hz and -70dbc/hz at 100hz. so how to write it into noise_table? I write it as noise_table({10,-60,100,-70},"noitab"); Is it right? If it is wrong, how to describe it? thank you!
  6. I

    SRAM SNM Simulation - Hspice

    I was wrong yesterday......your code greatly helped me! Thanks! And I get the reason which u found. SNM is static noise margin, so u can't run tran simulation to get SNM. u should run dc simulation by sweep the noise voltage. I have tryed it. The two methods have the same results.
  7. I

    SRAM SNM Simulation - Hspice

    I think that the Trail_and Error method does not follow the definition of SNM unless you remove one of the noise voltage source from the schematic.
  8. I

    [SOLVED] parametric analysis problem

    Hi, all. I am simulating a band gap reference. It have four pins to do current trim. When I sweep these four pins by parametric analysis tool, It gives me a different result from ordinary(change the pin's signal by manual) simulation. I am puzzled by it, and I confirm the setting is right...
  9. I

    [SOLVED] efficiency of a dc-dc

    thank you ,all. I found the reason why the efficiency I simulated was above 100%. It is my fault. I calculated the efficiency too early when the system is not steady.Thanks again.
  10. I

    [SOLVED] efficiency of a dc-dc

    thanks again,FvM. But when I use the calculator in the candence to measure the Iavg, I found the efficiency >100% in small load current. Then I think this method is questionable.
  11. I

    [SOLVED] efficiency of a dc-dc

    thank you, FvM. What you said is very helpful for me. I also found that when I used Irms instead of Iavg, the efficiency was lower. There is still a question: when the load current is very small, current flowing through the inductor will be reversed. Then the Iavg is incorrent to calculate the...
  12. I

    [SOLVED] efficiency of a dc-dc

    thank you for your reply, manojdharap. I am a beginner of dc-dc convertor, so I am just simulating a basic current mode one and it is integrated except L, C, compensation net. there are current sensing circuit, osc, comparator, driver and so on. these control circuits' power is constant. I can't...
  13. I

    [SOLVED] efficiency of a dc-dc

    hello,all. i'm simulating a buck dc-dc by candence, and i am not sure how to measure the efficiency. someone told me measure the rms of input current, then multiply vdd, and this is input power. but i don't understand, why rms, not average? and another question is the other control part's of...
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