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Recent content by Ian Bond

  1. I

    VHDL code for storing 3 different values in memory.

    I am unable to get the output even for 32 bits. Please refer to the first post.
  2. I

    VHDL code for storing 3 different values in memory.

    I tried it. It was not working. Please suggest some changes.
  3. I

    VHDL code for storing 3 different values in memory.

    I attached the code for 32 bit input. If this works, I can extend it to 64 bits.
  4. I

    VHDL code for storing 3 different values in memory.

    Hello, I am doing a project which involves writing 3 64 bit signals in memory and reading them later. My code has a 64 bit data_in, a 64 bit data_out, clock, an address1 signal, address2, address3 signal, Output enable, write enable and read enable signals. The input is given...
  5. I

    reading from the Altera DE1 SRAM in VHDL

    [Is there any other way to transmit the data to the DE1 board from my computer other than the Control panel software?
  6. I

    reading from the Altera DE1 SRAM in VHDL

    Hello, Can you please elaborate the multiplexing part. Also can you please tell me which exact signals to multiplex... I can attach the codes if you want to take a look at them.....
  7. I

    reading from the Altera DE1 SRAM in VHDL

    Hello, As far as I know, the SRAM on a DE1 baord is Asynchronous. So, from the above what I understood is I need to include the verilog file corresponding to the Control Panel software in my project(in Quartus 2) and instantiate that component with the signals data bus, address bus...
  8. I

    reading from the Altera DE1 SRAM in VHDL

    FvM proposed the following solution in a different thread. "Reading SRAM is very easy. Just put the address to the data bus, assert /CE, /OE, /LB and /UB and read the data one clock cycle later." Can you please explain this to me. I am unable to figure this out.
  9. I

    reading from the Altera DE1 SRAM in VHDL

    Hi, SRAM_DQ, // SRAM Data bus 16 Bits SRAM_ADDR, // SRAM Address bus 18 Bits SRAM_UB_N, // SRAM High-byte Data Mask SRAM_LB_N, // SRAM Low-byte Data Mask SRAM_WE_N, // SRAM Write Enable SRAM_CE_N, // SRAM Chip Enable SRAM_OE_N, // SRAM Output...
  10. I

    reading from the Altera DE1 SRAM in VHDL

    So, should I include the .v file corresponding to the control panel software in my project in Quartus 2 and write a code to link this file to my code?
  11. I

    reading from the Altera DE1 SRAM in VHDL

    Hello, Thanks for the reply. I have one more question. After compiling my code in Altera Quatrus 2, I have a .sof file generated which I need to dump onto the DE1 board. But I also have a .sof file for the control panel software as well. So, if I need to use the control...
  12. I

    reading from the Altera DE1 SRAM in VHDL

    Hi everyone, I am doing a project which involves storing 3 64 bit values on the SRAM of a DE1 board and using them later. I am using the DE1 control panel software to write the values onto the SRAM but I am unable to figure out how to read those values to use them in my code...
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