reading from the Altera DE1 SRAM in VHDL

[Ian Bond]

Hi everyone,
I am doing a project which involves storing 3 64 bit values on the SRAM of a DE1 board and using them later. I am using the DE1 control panel software to write the values onto the SRAM but I am unable to figure out how to read those values to use them in my code.
I would really appreciate it if someone can help me out with this problem.

 

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Seems like you have the same problem as this poster.

https://www.edaboard.com/threads/124285/

FvM gives the solution without giving specific details.

Basically write some code to generate the address, output enable, read enable for the SRAM and have those ports hooked up to the pins of your FPGA that are connected to the SRAM. If the RAM is synchronous you'll have to use the same clock as the RAM uses to read. If it's an asynchronous RAM then supply address/enables to the RAM and wait longer than the access time to capture the data.

Regards

 

[Ian Bond]

Hello,
Thanks for the reply. I have one more question.
After compiling my code in Altera Quatrus 2, I have a .sof file generated which I need to dump onto the DE1 board. But I also have a .sof file for the control panel software as well. So, if I need to use the control panel software with my code, do I need to dump both of the .sof files onto the board?

 

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You can only use one sof file at a time. The sof contains all the configuration programming bits for the entire FPGA.

Regards

 

[Ian Bond]

So, should I include the .v file corresponding to the control panel software in my project in Quartus 2 and write a code to link this file to my code?

 

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Yes.

Didn't realize you had the Verilog for the control panel. Depending on how the control panel file is implemented you might have to instantiate your code in the control panel file. Look for things like instantiated io cells for starters

 

[Ian Bond]

Hi,

SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable

I found these signals corresponding to the SRAM in the verilog file of the control panel. So, can you tell me what to do with these?

 

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They connect to the pins that are attached to the SRAM. You have to add some logic like a multiplexer to switch between the control panel logic driving the address and control and your logic.

Regards

 

[Ian Bond]

FvM proposed the following solution in a different thread.

"Reading SRAM is very easy. Just put the address to the data bus, assert /CE, /OE, /LB and /UB and read the data one clock cycle later."

Can you please explain this to me. I am unable to figure this out.

 

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FvM was describing the protocol for reading SRAM (static RAM). For asynchronous SRAM you need to apply the address to the address pins, assert /CE and /OE and wait for the access time of the RAM before capturing the data. If the RAM is synchronous then you will likely have to capture the data one clock cycle after applying the address and control on the previous clock edge.

You could have pulled a datasheet for an SRAM device and looked at the timing diagrams for read operations.

Regards

 

[Ian Bond]

Hello,
As far as I know, the SRAM on a DE1 baord is Asynchronous. So, from the above what I understood is I need to include the verilog file corresponding to the Control Panel software in my project(in Quartus 2) and instantiate that component with the signals data bus, address bus, CE, OE, LB, UB in my code and program accordingly. Am I correct?

 

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You need to multiplex the signals to connect your FPGA logic and the control panel logic (Verilog) together, as they will be sharing the SRAM interface. The control panel logic will write the 64-bit values into the SRAM and your code will read the 64-bit values from SRAM, which means which module controls the SRAM will change.

 

[Ian Bond]

Hello,
Can you please elaborate the multiplexing part. Also can you please tell me which exact signals to multiplex... I can attach the codes if you want to take a look at them.....

 

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a mux

assign sram_addr = use_ctrl_panel ? SRAM_ADDR : ian_bond_logic_sram_read_addr;

How you determine which address is selected depends on the use_ctrl_panel. How you generate the signal, well you have to decide and come up with a solution.

Personally I would junk the control panel and generate the data in the FPGA or transmit the data to the FPGA through a UART/SPI/Ethernet/etc.

Regards

 

[Ian Bond]

[Is there any other way to transmit the data to the DE1 board from my computer other than the Control panel software?

 

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[Is there any other way to transmit the data to the DE1 board from my computer other than the Control panel software?

Yes there are but most will require significantly more design work on your part.

I recommend using the control panel as it's only 3 64-bit values. You need to find a way using either the control panel or a HW pin (switch) to select the control panel or your FPGA logic accessing the SRAM, hence the need for a mux to select which has control.

Regards