Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: job hunting
It's tough time in US, especially in Silicon Valley, too many guys got layed off, almost 100:1 for one opening, and the war made the situation even worse. Although you are good enough, but how can HR guys identify you from that many candidates? I am not sure whether there...
7years experience, mature enough to handle the following design, young enough to chanllenge the high-end, multi-million, timing critical designs.
**broken link removed**
hierarchical design methedology.
die size: 9x9
pins: more than 400
clock: 12 clock domains
main freq: 240M
foundry...
job hunting
Hi, all
I know it's not a right place to post, sorry for any inconvenience.
For some reason, a SR. ASIC Design engineer is looking for an ASIC Design opptunity. currently I live in Silicon Valley,ca,US. have almost ten chips successfully tape-outs(under .18, timing...
Job hunting
Hi, all
Looks like it's the first post in the forum. For some reason, a SR. ASIC Design engineer is looking for an ASIC Design opptunity. currently I live in Silicon Valley,ca,US. have almost ten chips successfully tape-outs(under .18, timing critical) including some big chips...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
