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rf pcb design
Hai Folks:
I tested my mixer and QVCO using wafer probing, but whenever I mount it on the PCB (duriod), with off chip balun, the device fails. Can you give me some pointers on RF PCB design and highlight any dedicated steps to test each of the block. Any reading materials would...
why positive phase noise?
Hai Folks:
I had jumped across a similiar inquiry in the Designer's Guide forum. According to Ken Kundert, the author of Designer's Guide to Spice and Spectre, the low fequency corner in the phase noise response is caused by large signal effects and the simulator...
pss saveinit
Hai Folks:
I had simulated the phase noise of a LC-QVCO using cadence spectreRF, with a pulse source perturbation. But I'm getting positive phase noise for offset frequency less than 100Hz. I thought the phase noise plot is a normalized plot of the carrier. It should start from 0...
Hi Guys:
I would appreciate if you could pass me the journals:
1. M. Park, S. Lee, H. K. Yu, J. G. Koo, and K. S. Nam, "High Q CMOS-compatible microwave inductors using double-matter interconnection silicon technology", IEEE Microwave Guided Wave Lett., vol. 7, pp. 45-47, Feb. 1997.
2. P. J...
Hi Guys:
I had laid out a pMOS transistor with grounded dummies poly (gate) as etch guards to reduce mismatch. With reference to the attached figure, I had connected the dummies using metal in a loop surrounding the pMOS transistor. I had read that placing dummy in a continuous ring poly could...
Hai Guys:
I had designed an error amplifier for dc biasing purpose. The stability of the design shown in plot (Stb1.jpg) and plot(Stb2.jpg), are in the range of 60-90 degrees in terms of the phase margin. But I had also been informed that the zero and the second pole shouldn't be located...
Hi Guys:
I often come across in situation of determining the transient stability in BGR design as a requirement. Since the ac stability analysis only potray the small signal analysis.
Usually a Vpwl is applied to the Vdd to be ramped from 0v to Vdd, and the output is cross checked whether it...
A symmetry differential architecture can minimize flicker noise up-conversion, as unbalanced oscillator results in 2ω common mode oscillation, which is mixed with fundametal oscillator frequency, resulting in phase noise at the oscillator frequency. Hope this helps....
Rgds[/list]
Hi Guys:
I need some help in the design of the prescaler circuit for my VCO. I find many journals proposing circuit such as ILFD (Injection locked frequency divider) or a commonly used static master-slave flip-flop based frequency didivder. Based on the theory I understand the former...
Re: LC VCO
Hi:
I understand that LC-VCO in complementary form gives a higher gm for the given current consumption, moreover is draws less current compared to single cross coupled -gm LC-VCO.
In a top biased pMOS VCO the loading parasitic of the resonator is referred tovGnd hence enhances the...
Thnx for your explanation, it is stated in a foundry design manual an ESD power clamp is required if the capacitance is less than 100nF betweed Vdd and Gnd. Is it possible to avoid this clamp if I place a MOS cap between Vdd and Gnd, with capacitance more than 0.1pF?. Thanks in advance
Rgds
Hi Guys:
When I design the RF circuit, I would include a reversed biased diode model at the I/O port for surge protection. This is illustrated in Figure.1 where a complete I/O model used is presented.
I had received a feedback for an ESD designer to increase the number of series connected...
Thanks for your replies,so reversed biased diode ESD protection is only used in the input-output pins, and hence it is not essential to place it on each of the gate of the transistors in the circuit, Is it true?. Pls shed some light on this issue.
Thanks in advance
Rgds
Is it a normal practice?, if I have an output terminal from the gate to control the voltage of the circuitry, is it advisable to insert this reversed biased pn junction?. Thanks in advance.
Rgds
Hi Guys:
When I submitted the GDSII file to the foundry, they feddback me in adding a reversed pn junction diode to GND at each gate transistor used. I thought adding a reversed biased diode to VDD and GND is only needed at the Input -Output of RF circuitry, please feedback whether it is...
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