hrkhari
Full Member level 4
Hi Guys:
When I design the RF circuit, I would include a reversed biased diode model at the I/O port for surge protection. This is illustrated in Figure.1 where a complete I/O model used is presented.
I had received a feedback for an ESD designer to increase the number of series connected diodes to decrease the effective capacitance at the I/O for RF signals, is it advisable to do so?.
I had also received an advise from the foundry to include a p-n junction reversed biased diode at each of the transistor gates in the circuit ad in Figure. 2. Is it advisable to do so?. Would it effect the performance of the designed circuit?.
I highly appreciate your kind assistance. Thanks in advance
Rgds
Harikrishnan
When I design the RF circuit, I would include a reversed biased diode model at the I/O port for surge protection. This is illustrated in Figure.1 where a complete I/O model used is presented.
I had received a feedback for an ESD designer to increase the number of series connected diodes to decrease the effective capacitance at the I/O for RF signals, is it advisable to do so?.
I had also received an advise from the foundry to include a p-n junction reversed biased diode at each of the transistor gates in the circuit ad in Figure. 2. Is it advisable to do so?. Would it effect the performance of the designed circuit?.
I highly appreciate your kind assistance. Thanks in advance
Rgds
Harikrishnan