Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Of course i do expect that behavior, but the simulation speed is getting even more slower over runtime. After some milliseconds simulation time the worst effect is reached with 20ns simulation time per Realtime Second!
I got some problems with my VCS-MX simulation, which massively slows down after running some million cycles. My Setup:
SV Testbench
VHDL unit under test
binded SVAs to some VHDL submodules
Compiled with: vcs -debug_pp -sva_bind <bind_file> -assert dumpoff <toplevel>
Does anyone knows...
I've a question regarding PSL assertions within VHDL code. Thats my testcase entity:
entity Test is
port(start_i : in std_logic;
size_i : in std_logic_vector(2 downto 0);
);
Now I want to setup a property that guarantees a stable input size_i for at least 3 clock cycles before...
Now it gets weird. I did what you advise me:
read_ddc -netlist toplevel.ddc
current_design toplevel
link_design
-> Loading db file '/TSMCHOME/digital/Front_End/timing_power_noise/CCS/tcbn90ghp_210b/tcbn90ghpwc_ccs.db'
-> Linking design toplevel...
-> Warning: Unable to resolve reference to...
Hello everyone,
I did a synthesis of my design with the Design Compiler and Formality signals me that all compare points are equal (*.ddc vs. RTL). Also its possible to read back the ddc file with DesignVision and generate some schematics. But when I read my design into Primetime by typing...
If you use the design compiler for synthesis you need to activate the generation of a *.svf helpfile (contains all optimizations, renamings,...) that is necessary to find "compare" points.
Then you read in the synthesized netlist and of course the reference design (vhdl or verilog source) and...
Thanks for your reply. This seems to be the root of the problem!
If I compare the timing for the same path in DC and PT there are small differences in the cell delay. This is the DC output of "report_timing -delay_type max_rise" -from reg[0] -to reg[1]
reg[0]/CP (EDFCNQD2)...
I don't get it :sad:
I resynthesize my design without a clock latency to avoid syntax problems as hairo mentioned in his post. The timing report in DC shows this path:
Operating Conditions: WCCOM Library: tcbn90ghpwc_ccs
Wire Load Model Mode: top
Startpoint: reg[0]
(rising...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
