[SOLVED] PSL Assertion - stable()

[hbeck]

I've a question regarding PSL assertions within VHDL code. Thats my testcase entity:

entity Test is
  port(start_i : in  std_logic;
        size_i  : in  std_logic_vector(2 downto 0);
  );

Now I want to setup a property that guarantees a stable input size_i for at least 3 clock cycles before start_i is pulled to '1'. My first try was the usage of stable(), unfortunately this function covers only the last cycle. For 3 clock cycles I need three stable calls which seems to be pretty awkward if there is a requirement for 'more' stable cycles.

  -- psl default clock is (clk'event and clk = '1');
  -- psl A1: assert (always start_i |-> stable(size_i));
  -- psl A2: assert (always start_i |-> stable(stable(stable(size_i))));

So is there another way to describe this property?

Thanks for any help!

 

[hbeck]

I solved the problem by myself. (now its SVA)

 property p;
  !$stable(size) |-> !start[*3];
 endproperty