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Recent content by hawks4peace

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    question reg RTL coding

    Thanks for the reply. I couldn't understnd the concept properly. Can you please explain it in more detail or if u know a source or website can you please guide me to it. regards
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    Consultancies in the field of VLSI in USA

    Hello I am a MS graduate searching for jobs as a frehser in the field of VLSI. Does any one know any consultancies in the field of VLSI in USA? If so can you give me the contact info. Thanks
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    question reg RTL coding

    Hello Can any one tell me what is the difference between Register Transfer Level (RTL) style coding and normal HDL coding. I mean is there any difference at all or is it just a structural coding of logic diagram (combinatorial cloud and register pairs). Thank you for your help
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    Help regarding TimingDesigner :cry:

    Hello Does any one use TimingDesigner s/w. if so plzz help me... I have to use TD to check my design. The design is represented in structural VHDL code and synthesised using Xilinx ISE. I have to back annotate the timing checks and constraints of my design. I generated the .sdf file from ISE...
  5. H

    setup and hold times in Virtex 2 FPGA

    Hello Everybody I am working on Virtex2 libraries in another software. I couldnt find any setup and hold timings between the select line and inputs in a mux. I could locate the delays b/n inputs and outputs but dont know whether there are any setup and hold times for combinational logic like...
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    How to run ngc2edif utility in xilinx ISE 8.1i?

    ngc2edif xilinx i too have the same problem i tried ngd2edif in ise 6 command terminal and it says "The ngd2edif program and generation of back-end EDIF netlist for simulation is no longer supported in the current software. Please use netgen program to generate Verilog or VHDL netlists for...
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    help with .edf files and .edn files

    edf edn hello friends does anyone know which application produces .edf files (EDIF).. Xilinx produces .edn files but i need .edf extension. does anyone know how to convert .edn extension to .edf extension thanks
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    reg Timing Designer software and Xilinx V2 FPGA's

    hai can any one tell me how timing designer software is used for modeling and analyzing timing parameters in xilinx v2 fpgas. or what exactly in xilinx FPGA gets programmed when synthesizing a VHDL program in xilinx fpga i mean is it the clbs or block ram or multiplier. i need to know that...
  9. H

    implementing Nor gate using cmos transmission gates

    and gate implementation using transmission gates hi frens can anyone tell me how to implement nor gate using cmos transmission gate... urgent!!!
  10. H

    Pseudo two phase non overlapping clock generator...help

    hi frens... can anyone plz tell me how to construct a pseudo two phase non overlapping clock generator using cmos transmission gates or using 2 input nor gates...
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    Four-bit long, four-bit wide bidirectional dynamic shift register

    help needed urgent it has to b implemented in cmos n right now we r tryng a layout for it.. the circuit has about 130 transmission gates....
  12. H

    Four-bit long, four-bit wide bidirectional dynamic shift register

    Re: help needed urgent iam sorry, i dont want to bother u but here is the title of my project and i think it has a lot of twists..... please look at it and help me.. A four-bit long, four-bit wide bidirectional dynamic shift register circuit, without parallel inputs and without parallel...
  13. H

    Four-bit long, four-bit wide bidirectional dynamic shift register

    Re: help needed urgent i want to know what 4 bit long 4 bit wide means first of all bcos i didnt understand what it is.. and what does dynamic shift register means.. i mean the significance of word dynamic... i was given this project n i didnt understand anything abt this.. so please help me
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    Four-bit long, four-bit wide bidirectional dynamic shift register

    want information abt A four-bit long four-bit wide bidirectional dynamic shift register
  15. H

    please help very urgent vhdl code

    vhdl code for QR decomposition using givens rotation... calculate the weights using above algorithm[/url]
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