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Hello,
I am thinking of using a simple power sequencing chip from Ti, LM3880, to toggle the enable pins for a few voltage regulators. I posted the block diagram above. The chip's operation is quite simple. You toggle an enable pin and you get the following timing diagram for the three flags...
I had a question about how much the transmission line to IC transition would affect my design in folks' prior experience. Typically when we make high frequency (up to 18 GHz) PCBs we use rather thin substrates (8 mil) and SMA end launch connectors with fairly thin center pins to match our...
Thanks all. Pretty obvious its in reverse bias under normal operation.
Final question before making as solved. It seems that diode can be any general purpose Si diode? We have some 1N4148s around the board in other places, i assume that would suffice. The particuar one we are using has a...
Hello all,
This may be a dumb question, but, I am looking at a adjustable linear voltage regulator, BD00FC0WFP. Above is a picture of the recommended layout, a separate document from the datasheet. The datasheet has short paragraph of the diode's purpose:
I'm not sure what situations would...
Thanks for the reply. Thankfully Im not dealing with a FPGA, simply some RF components: ADRF5044 (SP4T), ADRF5730 (variable attenuation). But you are 100% spot on with dumping current through the protection diodes. Espeically if you apply any of the digitial control signals before Vdd...
Hello all,
I am trying to implement a simple power supply sequencing that I saw on an ADI article. The picture above shows what I am trying to recreate. My timing requirements aren't strict, I simply need my positive rails turn on before any negative rail and the negative rails to turn off...
That did it. I added a dummy port with nothing connected on the sheet symbol and it worked. Thanks to both! the same answer was given in the form linked above. I intially tried that solution but neglected to re-validate / compile the project didn't notice that solution worked.
Hello all,
I have a very simply schematic I wanted to repeat a few times in Altium 22.
I created the schematic I wanted to repeat, I then placed a sheet symbol on a higher level sheet and used the repeat function.
The sheet symbol changed to the graphical representation that it repeated...
Couple of reasons. My oscilloscope only has 50 or 1Mohm terminations. The eval board for the LMK04208 uses SMA end launch connectors. The eval board data sheet ( or user guide ) suggests so:
Sadly though, I'm no where near the 1 GHz BW or 10 Gsps rate :cry:
Sadly the user guide doesn't...
Hello all,
Thanks for the replies, very helpful. Quick follow up if you don't mind. If I am understanding your replies and the LMK04208 datasheet correctly. If I use the LVDS type output I can use the diagram above and achieve proper termination? The connection between the 100 ohm resistor and...
Hello all,
I am wondering what's the proper way to terminate a differential clock signal through a transformer into a single ended reference for a PLL. I've read through a few Ti application notes on the issue, but I am still a bit confused. The picture above is the diagram of what I am trying...
Hello all,
I am attempting to construct a circuit which will both cancel one of the upconverted sidebands as well as suppress any leaked LO. I've had good success in some ideal simulations but I had a few questions I wanted to ask before moving forward simulating some real components.
To build...
Hello all,
I am working to design a duel pll clocking scheme and I am playing around with Ti's PLLatinum software and ADI's ADIsimPLL software. In order to design the first PLL which uses a VCXO as the oscillator I need to know certain parameters of the VCXO. The first parameter I need to know...
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I don't do much PCB work, i guessed that's what's normally done. But looking at some of the RF eval boards we have, both the via fences and ground vias for a chip's exposed pads are through holes. I suppose I thought having what amounts to an added 1.2mm open stub would affect the results. But...
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