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conversion gives error code is
stdtst.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package intest is
subtype bits is std_logic_vector(7 downto 0);
function bconv(bits: std_logic_vector) return integer;
end package intest;
package body intest is
function...
if u r talking about the bit'pos() function so it is builtin and use to find the bit position.i have solve the problem by removing the variable temp: bit_vector(bits'range); but the other problem raised during simulation. and that is b takes the initial value from the component "alu" is driving...
i have written code in vhdl for conversion of bit_vector to integer but it always gives me 0 when simulate in modelsim.
code for the package is
alupack.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package aludgn is
function...
i am trying to make an alu but i am in initial stage. please help me ; i wrote the alupack.vhd file which gives me no error during compilation. code is here
library ieee;
use ieee.std_logic_1164.all;
package alu_types is
subtype bits_32 is std_logic_vector(31 downto 0);
---type bit_array is...
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