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conversion from bit_vector to integer problem

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hastnagri

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i have written code in vhdl for conversion of bit_vector to integer but it always gives me 0 when simulate in modelsim.
code for the package is
alupack.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package aludgn is
function bit_to_int(bits: in bit_vector) return integer;
end package aludgn;

package body aludgn is
function bit_to_int(bits: in bit_vector) return integer is
variable temp: bit_vector(bits'range);
variable result: integer:=0;
begin
for index in bits'range loop
result := result*2 + bit'pos(temp(index));
end loop;
return result;
end function bit_to_int;
end package body aludgn;
////////////////////////////////////////
alufunc.vhd is
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.aludgn.all;
entity alu is
port(val: in bit_vector;
result: out integer);
end entity alu;
architecture behav of alu is
begin
bv: process is
begin
result<= bit_to_int(val);
wait for 5 ns;
end process bv;
end architecture behav;
//////////////////////////////////////
Test bench for the conversion is alustm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.aludgn.all;

entity aludesign is
end entity aludesign;

architecture behav of aludesign is
signal a: bit_vector (3 downto 0);
signal b: integer :=0;
begin
dut: entity work.alu(behav)
port map(a,b);
stim:process is
begin
a<="1010";
wait for 5 ns;
a<="0101";
---wait on a;
end process stim;
end architecture behav;
/////********/////////
code does not give any error while compiling but the problem occur when i simulate it, always gives zero (val=1010 and result=0) and value of "a" 1010 does not change to 0101 during simulation.
 

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FvM

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Two comments:
- bit is an undefined variable in the function, so 0 result isn't surprizing
- conversions of this kind are available with the IEEE libraries. You don't need to re-invent the (square) wheel.
 

hastnagri

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if u r talking about the bit'pos() function so it is builtin and use to find the bit position.i have solve the problem by removing the variable temp: bit_vector(bits'range); but the other problem raised during simulation. and that is b takes the initial value from the component "alu" is driving the value of b, so its initial value of 0 is overriden
 

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FvM

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if u r talking about the bit'pos() function so it is builtin
'pos() is a predefined VHDL attribute
bit is a standard type, just a single bit, and not redefined in your code. So bit'pos() seems pretty useless.
 

TrickyDicky

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you didnt attach the simulation results. How long did you run the simulation for? you realise that b is going to be 0 for the first 5 ns right?

I can see why you've bit'pos - it should work.

But I agree with FvM - this is one of the most overengineered solutions to a problem that has a solution already provided by the IEEE.
1. Why are you using bit_vectors? the IEEE provides a sultion for what you are trying to do but with std_logic_vector (or even better, unsigned or integer).
2. the "alu" entity is a waste of your time and text space - it does nothing except delay a signal
3. I hope you're not going to try and synthesise this.
 

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