#### hastnagri

##### Newbie level 4

i have written code in vhdl for conversion of bit_vector to integer but it always gives me 0 when simulate in modelsim.

code for the package is

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

package aludgn is

function bit_to_int(bits: in bit_vector) return integer;

end package aludgn;

package body aludgn is

function bit_to_int(bits: in bit_vector) return integer is

variable temp: bit_vector(bits'range);

variable result: integer:=0;

begin

for index in bits'range loop

result := result*2 + bit'pos(temp(index));

end loop;

return result;

end function bit_to_int;

end package body aludgn;

////////////////////////////////////////

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use work.aludgn.all;

entity alu is

port(val: in bit_vector;

result: out integer);

end entity alu;

architecture behav of alu is

begin

bv: process is

begin

result<= bit_to_int(val);

wait for 5 ns;

end process bv;

end architecture behav;

//////////////////////////////////////

Test bench for the conversion is

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use work.aludgn.all;

entity aludesign is

end entity aludesign;

architecture behav of aludesign is

signal a: bit_vector (3 downto 0);

signal b: integer :=0;

begin

dut: entity work.alu(behav)

port map(a,b);

stimrocess is

begin

a<="1010";

wait for 5 ns;

a<="0101";

---wait on a;

end process stim;

end architecture behav;

/////********/////////

code does not give any error while compiling but the problem occur when i simulate it, always gives zero (val=1010 and result=0) and value of "a" 1010 does not change to 0101 during simulation.

code for the package is

**alupack.vhd**library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

package aludgn is

function bit_to_int(bits: in bit_vector) return integer;

end package aludgn;

package body aludgn is

function bit_to_int(bits: in bit_vector) return integer is

variable temp: bit_vector(bits'range);

variable result: integer:=0;

begin

for index in bits'range loop

result := result*2 + bit'pos(temp(index));

end loop;

return result;

end function bit_to_int;

end package body aludgn;

////////////////////////////////////////

**alufunc.vhd**islibrary ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use work.aludgn.all;

entity alu is

port(val: in bit_vector;

result: out integer);

end entity alu;

architecture behav of alu is

begin

bv: process is

begin

result<= bit_to_int(val);

wait for 5 ns;

end process bv;

end architecture behav;

//////////////////////////////////////

Test bench for the conversion is

**alustm.vhd**library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use work.aludgn.all;

entity aludesign is

end entity aludesign;

architecture behav of aludesign is

signal a: bit_vector (3 downto 0);

signal b: integer :=0;

begin

dut: entity work.alu(behav)

port map(a,b);

stimrocess is

begin

a<="1010";

wait for 5 ns;

a<="0101";

---wait on a;

end process stim;

end architecture behav;

/////********/////////

code does not give any error while compiling but the problem occur when i simulate it, always gives zero (val=1010 and result=0) and value of "a" 1010 does not change to 0101 during simulation.