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Recent content by haoshs

  1. H

    low power comparator design for SAR ADC

    offset is a random variable. It's different from chip to chip, or die to die.
  2. H

    Intrinsic gain simulation

    arvkp123: How to get the intrinsic gain? THX
  3. H

    drain-source conductance gds

    Just as hyc said, the gds value of simulation is far small. that is 75e^-9, however, the intrinsic gain is only about 20(meg) for gm = 123uS So, what kind of method is it to evalulate the intrinsic gain?
  4. H

    buffer spec for sigma-delta modulator or sc filter

    I want to know the question also. Especially the driver spec of buffer. THX ad.
  5. H

    settling of SC integrator

    what is exactly the reason for overshoot?
  6. H

    OpAmp design for SC-integrator

    I also have the same question: "Is the the GBWP of 5MHz enough for the 50MHz sample frequency? ". In my opinion, the GBWP should be at least 5 times fclock, that is 25MHz.
  7. H

    about chop amplifier frequency

    Hi FvM: How to get the " CMOS noise corner"? Thinks!
  8. H

    How to simulate Crystal Oscillator in HSPICE?

    oscillator transient crystal Seting delmax is great idea. it really works. TX
  9. H

    Error in ICFB window of IC5141 on FC7

    ic5141 I also install IC5141 on FC7. And it works well. I donot occur the problem. please list your .cshrc file
  10. H

    Mentor Calibre linux issue

    ld_assume_kernel 2.4.1 + rhel5 I found it thank you but when I open a help webpage in cdsdoc, there is also the massege like following: Copyright © 2000-2003, Cadence Design Systems, Inc. libgcc_s.so.1 must be installed for pthread_cancel to work Anyone can help me! Thanks a lot
  11. H

    Mentor Calibre linux issue

    install calibre rhel 5 Hi, okguy Where is calibre.env ? I cann't find it in my install directory. thanks
  12. H

    problem about cadence~~~~

    just replace the tar with a old version, the problem can be solved. good luck
  13. H

    wide input range of LDO

    you can apply a depletion MOS transistor as a current source independence the voltage.
  14. H

    Question on Cadence simulation

    you do not care for that. it's warnings. maybe the convergence error occurs at the instant of power up.
  15. H

    LDO gain & phase margin

    From the PM plot, the PM is about 30 degree. I don't think the stable when process parameters or temperture varys.
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