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Hello,
I'm struggling to get a pre-layout power estimation with PrimeTime.
While I've been tried to solve the following warning, I've found that the problem came from the constraints about defining input port drive strength...
To figure out this problem, I've designed another simple DFF module.
The detailed information is as follows.
However, I still cannot find where this problem came from and how to fix this.
Please help me out...
Sorry but I can't understand what you meant.
I tried to calculate power just after synthesis and gate-level simulation. I've not done PnR yet.
(I synthesized my design in Topographical Mode though.)
This is my first time for gate-level simulation and PrimeTime power cacluation.
Could you...
Hello,
I've been trying to calculate average power with PrimeTime PX.
I designed a simple FF in Verilog and synthesized it with DesignCompiler Topographical mode.
After synthesis, when I simulate the netlist with SDF annotation, I've got following warnings...
Re: PrimeTime Warnings ("check_power" command)
Yes, I wanna fix those violations.
Could you tell me the way to fix those?
- - - Updated - - -
Yes, I wanna fix those violations.
Could you tell me the way to fix those?
Hello,
How can I fix those warnings below?
==========================================
pt_shell> check_power
Information: Checking 'out_of_table_range'.
Warning: There are 8395 out_of_range ramps.
Warning: There are 75 out_of_range loads.
Information: Checking 'missing_table'.
Information...
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