Warnings in gate-level simulation

[Hanul]

Hello,

I've been trying to calculate average power with PrimeTime PX.

I designed a simple FF in Verilog and synthesized it with DesignCompiler Topographical mode.

After synthesis, when I simulate the netlist with SDF annotation, I've got following warnings.

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$recovery (posedge RSTB,posedge CLK &&& (D==1'b1),tsu_rstb_h_clk,notifier);
|
ncelab: *W,SDFNL1 (/usr/eda/synopsys/lib/SAED_EDK90nm/Digital_Standard_Cell_Library/verilog/saed90nm.v,4811|9): Attempt to annotate a negative value to a 1 limit timing check in instance (tb_my_dff.u_my_dff.\ff_reg_reg[0] ), setting to 0 </home/Hanul/temp/dff/syn/sdf/my_dff.sdf, line 45>.
ncelab: *W,SDFNET: Unable to annotate to non-existent timing check (HOLD (posedge RSTB) (posedge CLK) (0.134)) of instance tb_my_dff.u_my_dff.\ff_reg_reg[0] of module DFFARX1 </home/Hanul/temp/dff/syn/sdf/my_dff.sdf, line 46>.
$recovery (posedge RSTB,posedge CLK &&& (D==1'b1),tsu_rstb_h_clk,notifier);
|
ncelab: *W,SDFNL1 (/usr/eda/synopsys/lib/SAED_EDK90nm/Digital_Standard_Cell_Library/verilog/saed90nm.v,4811|9): Attempt to annotate a negative value to a 1 limit timing check in instance (tb_my_dff.u_my_dff.\ff_reg_reg[1] ), setting to 0 </home/Hanul/temp/dff/syn/sdf/my_dff.sdf, line 68>.
ncelab: *W,SDFNET: Unable to annotate to non-existent timing check (HOLD (posedge RSTB) (posedge CLK) (0.134)) of instance tb_my_dff.u_my_dff.\ff_reg_reg[1] of module DFFARX1 </home/Hanul/temp/dff/syn/sdf/my_dff.sdf, line 69>.
====================================================================================

Can somebody advise me how to fix these warnings?

Thanks in advance!

 

[Fahmy]

Attempt to annotate a negative value : usually occurs when you are not allowing the simulator to use negative timing checks while the sdf has some with negative values

Unable to annotate to non-existent timing check : usually occurs when the sdf timing arcs generated by the synthesis/back-end tool are not the same as that exist in the verilog model of the standard cell library. Some times you may need to write sdf files in different version. Sometimes you may need to enable some switches in the verilog model and sometimes you may need to change the arc name in the sdf file (e.g. change recovery to setup or removal to hold) .