Hanul
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Hello,
I'm struggling to get a pre-layout power estimation with PrimeTime.
While I've been tried to solve the following warning, I've found that the problem came from the constraints about defining input port drive strength.
===================================================================================================
ramp 0.00 at pin 'D' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'CLK' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'RSTB' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'D' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'CLK' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'RSTB' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
Warning: There are 6 out_of_range ramps.
===================================================================================================
Now, I fixed the warnings about "D" pins of the FF cell, but still don't know how to do with warnings about "clock" and "reset".
As far as I know, high fan-out nets such as clock should be considered as an ideal nets. (zero-resistance / zero-capacitance)
What should I do with those warnings above about "clock" and "reset"?
Thanks in advance.
I'm struggling to get a pre-layout power estimation with PrimeTime.
While I've been tried to solve the following warning, I've found that the problem came from the constraints about defining input port drive strength.
===================================================================================================
ramp 0.00 at pin 'D' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'CLK' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'RSTB' of cell 'ff_reg_reg[1]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'D' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'CLK' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
ramp 0.00 at pin 'RSTB' of cell 'ff_reg_reg[0]' is out of ramp range (0.02, 1.02) of lib_cell 'DFFARX1'
Warning: There are 6 out_of_range ramps.
===================================================================================================
Now, I fixed the warnings about "D" pins of the FF cell, but still don't know how to do with warnings about "clock" and "reset".
As far as I know, high fan-out nets such as clock should be considered as an ideal nets. (zero-resistance / zero-capacitance)
What should I do with those warnings above about "clock" and "reset"?
Thanks in advance.