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yes, Sone_2907 is right. But the kv usually is variable base on your structure, typical 1:3, so you can consider set Icp vs. kv in order to keep the BW constant.
if you want to using this LDO for RF VCO/PLL, I suggest that u must care the 1~100kHz output noise which will affect the close-in noise about pll/vco. It's really really true, but I don't think the MAXIM's 60uV is enough.
first, u must calc the spurious frequency for integer and frac. then u must calc the spuriou gain, every spurs from diff block have diff transfer factor. Finally, simulate it... In fact, we don't calc it usually. we just have good design in charge pump design, such as mismatch, leakage...
what is your comparison frequency fo PFD?2nd loop filter is enough.
Set the BW is 1/15 ~ 1/10 of Comp. freq. and phase margin is about 45 ~55 degree.
the Deans book is good reference 4 u.
1. need enough delay time for reset signal of PFD.
2. minimize the delay time of UP/DN.
3. minimize the setup time of source/sink current.
4. minimize the mismatch/leakage of source/sink.
5. delay time must be minimzed and large pulse width will increase spur.
yes,
1. check deadzone.
2. check mismatch and leakage of source/sink.
3. are u sure it's locked? loop isn't unstable?
4. I think PLL need this small phase different keep it in "locking".
1. Sperate power supply of VCO, CP, Divider.
2.Maybe add a Regulator to VCO's power. (Decrease pushing)
3. Add a lot of decoupling cap between vcc and gnd.
4. Add guard ring for each cell in layout.
hope it's useful!
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