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The equivalent gate count means ,what ever design u have that consists of mux,flops etc .If we convert that design into basic gates then whats the total no of gates taken.
I just want to add something ... As silencer said in scan compression the compression factor decide the length of the chain.But as we increase the compression factor the complexity of the circuit increases which further decreases the coverage ,so we have to take the trade off between compression...
There is a low impedence path occured inbetween Vdd and Vss.So because of that huge amount of current flows in the device and causes to destroy the device permanently.The avoide this latchup we use guardrings.
For mor details ple reffer Kang Digital VLSI deisgn.
how to draw stick diagram
hi
Stick dig is used to represent ur desing in differnt colour so that u can differntiate ur design that where is my metal line going on and where is poly and where is metal.There are many ways to draw a stick dig. After doing practice u can draw a optimize stick dig...
Re: FET and BJT question
If you look at the output characteristics of the FET & BJT, the active region of the BJT corresponds to the saturation region in a FET though they are referred with different names. So the BJT acts as an amplifier in the active region which happens to be the saturation...
race around condition in flip flops
In JK flip flop whne the value of J and K =1 and at the same time vlaue of clock is 1 ,so according to the truth table of J=k=1 the value of output should be toggled so the value keep on changing till the change in the clock pulse.which is not acceptable...
Re: CMOS
We connect substrate terminal NMOS to lowest potential and PMOS to highest potential because we need to reverse bias the drian source terminal with respect to channel and substrate and moreover if we do the reverse it will work as week buffer as when Vin =0 nmos will work and gives 1...
code coverage and functional coverage
Code Coverage Checks How your testBench covers the Statments,Expressions,
Conditions, Branches, Toggle Nodes in your Design Under Test.
Different TestBenches can target Different Statments in the Design Unit
Functional Coverage From its name it checks...
Yes in dft the sequential circuits are not scan able so we can't control and observe them .to meke them scanable we convert that sequential circuits into scan able flops by giving input through mux.
Re: hi plz can u tell the differe for 180 nm and 90 nm techn
HI
When we r talking about 180nm or 90 nm or any nm then it means that we r talking about the feature size so 90 nm meter the min size of the length of the transistor in that device is 90nm..
HI
Can u be elaborate ple in what sence u want to know about latch up problem?
Like in verlilog prog while the time of writting code we infer a latch and because of which we don't get the exact functionality...
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