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Hi Pavan,
1. Macros are aligned such that the pins, pin orientation, channel between memories, any extra spacing to be left around, their power source are taken care. Overall the macro placements have to give close to rectangular space for the standard cells. Secondary issues have to be taken...
Re: How to measure VIH at normal range 2.5V CMOS(JESD80,JESD
If you are running your spice simulation.. then you can sweep your input DC voltage from 0 to VDD and then check at what input voltage the output changes to High..
VIH is basically the min input voltage at your input pin that can...
U r question has lots of possibilities..
So r u lookin at porting them or designing in same technology node ??
If so watz the max freq of operation beyond 100 MHz ??
Do a simple tran.. measure the input cap of both the switches or just the second switch.. that can be considered as the load for the prev stage..and then resize your previous stage to meet ur timing.
Hi,
How do i measure the max value among a set of values say from n1 to n10... where n1 to n10 are the timing delays measured using a different measure statements..
like..
.mea tr n1 trig .... targ...
.mea tr n2 trig .... targ...
.mea tr n3 trig .... targ...
.mea tr n4 trig .... targ...
.mea...
Re: plz kindly help me out
These links should give you a clear picture...
http://www.datasheetcatalog.org/datasheets/134/500366_DS.pdf
**broken link removed**
Hope this helps...
If ppl are using the synopsys primetime tool already..
then i guess you have a tutorial in the path where the tool is installed/accessed from....
<Installed_path>/synopsys/pt/<version_no.>/doc/pt/tutorial/..
Just search in the dir structure and u shd b able to find the tutorial and the need...
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