combinational circuit design:RTL to GDSII

[joijac]

Dear all,

How can i give constraints to a combinational design in SDC format. wt all the RC commands and basic constraints for a combination design?

kindly help
Thankx in advance

 

[Goldeneagle]

I guess u can put an flop at the inputs and the outputs..
and constrain them using virtual clocks..

 

[salma ali bakr]

for constraining combinatorial logic, you don't need to associate input and output delays with a clock....it's the opposite of constraining sequential logic, where you always need to link your block with a clock

 

[xchuang19]

whether to create a virtural clock or not is determined by your system and interface requirement, u may think about the max delay and min delay .

 

[joijac]

thankx all...for repliess


i would like clear abt a basic combinational circuit like 7400,7432(gates),adders,multipliers,encoder.how can make .gds2 file for those designs without virtual clocks??

thankz in advance!!