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Recent content by gold_kiss

  1. G

    clock data recovery (all digital)

    hi fpga_asic_designer thanks, Ok my specs are BER of 10e-12, 0.4UI of jitter. Can you tell me how was your cdr? was it having any frequency correction? apart from phase? Thanks
  2. G

    clock data recovery (all digital)

    Hi all, anyone can give me all digital clock data recovery circuit for Gigabit rate, with BER of 10e-12
  3. G

    Any IC Design House in Denmark??

    ic design companies in denmark Vitesse Semiconductor Copenghegen
  4. G

    Cadence IFV training material

    ifv cadence Anyone has Cadence IFV training material.
  5. G

    Salaries in Stuttgart

    anyone staying in Frankfurt, Langen?
  6. G

    Dual port SRAM using 2 single port SRAM

    Thanks for your replies. But what I need is true Dual Port SRAM. In-a-sense read and write to two different ports can happen simultaneously. Wht explanation you have provided just adds the depth of SRAM kind of address concatination. Thanks, Gold_kiss
  7. G

    Dual port SRAM using 2 single port SRAM

    single port ram dual port ram Hi all, Anyone has designed Dual Port SRAM using 2 single port SRAM? Please give references. Thanks, Gold_kiss
  8. G

    Sharp 750D microwave service manual

    sharp microwave service manual Hi All, Anyone having Sharp 750D microwave service manual. Thanks, Gold_kiss
  9. G

    Why ICs color is black?

    Re: Why IC are black? This could be because of packaging material. Quite an interesting question though.
  10. G

    maximum frquency calculation ....

    T = Tpd + Tsu + Tcombo F(max) = 1/T If +ve clock skew between 2 flops then T = Tpd + Tsu + Tcombo - Tskew
  11. G

    Advantages of having positive slack

    Re: +ve Slack Positive slack is always better.
  12. G

    Xilinx part in India?

    Hi All, Can anyone tell me where can I buy Xilinx/Altera parts in India. Thanks, Gold_kiss
  13. G

    Clock domain crossing timing error

    You need to define false path for signal crossing from one domain to another.
  14. G

    Companies in Portugal

    Hi, Can anyone give me list ASIC companies in portugal?
  15. G

    Why designers write VHDL codes which include UNISIM components?

    Re: regd VHDL n UNISIM Hi, Basically Unisim contains simulation models of Xilinx internal elements. They are used to get exact behaviour of the elements as these will be then mapped during synthesis. Thanks, Gold_kiss
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