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Recent content by gmajay123

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    Why Transmission gate in FlipFLops

    Hi. The basic storage element in static Flip Flop is a pair of back to back connected inverters. If the inverters are named A and B, you have two nodes in the circuit o/p of A and o/p of B. A = !B 'A' can be zero or one based upon the noise in the circuit at power up. You need some kind of...
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    Command to save session in cadence RTL compiler

    Are there any commands in RTL compiler similar to synopsys's save_session and load_session.
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    What kind of ASIC designer is better off, frontend or backend?

    Re: Frontend vs. Backend Guys, Dont keep threatening BE Engineers that the backend flow will be completely automated and they will not be required. It will not be long before the Front End is automated. There will be tools which will convert C codes, FSM's( from a graphical view ) into HDL's...
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    Need some advise on changing my careee

    Hi. I have been working as a Digital Design Engineer for a year now. I always had interest in Analog Design and have also taken half a dozen courses in Analog Integrated Circuit design during my Masters. But i somehow landed up in digital design. Is it worth it to search and takeup a new job in...
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    Need of Function over Tasks in verilog

    Task is used as a statement. Function can be used in an expression i.e a function can be used instead of a constant value or variable.
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    Memory in scan testing

    I guess you can use some wrapper logic around a memory or analog block for better coverage in scan
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    Verilog Question about Always sensitivity list

    Hi. When modelling combinational logic we must make sure all signals that appear on the RHS of any assignment but be present in the sensitivity list, so that, when the signal changes the assignment is executed. Missing any signal in the sensitivity list "may" model a latch. So, to avoid a...
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    Metals used in IC fabrications

    Pure Aluminium, Copper, Silver
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    what are the reasons behind set up and hold time??

    1) Flipflop is back to back latches. for a +ve edge triggered flipflop you have a negative latch followed by positive latch. 2) Latch when implemented physically with transistors has some propagation delay. 3) In this case setup time is the propagation delay of negative latch. So when the...
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    Recent College Graduate position - ASIC Design, Digital/Anal

    Location : CA, USA must graduate this May or must have graduated after Dec 08 H1 will be Sponsored to F1 candidates Forward your resume, cover letter to gm.ajay.reddy@gmail.com Done send me mails after April 30th
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    Wide Swing cascode Doubt - please explain

    Wide Swing cascode Doubt What i know is both the rail devices should see the same drain voltage for better matching. But Why is the gate of M3 tied to Drain of M5.
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    quality factor of lowpass filter

    1)Quality factor for bandpass can be visualized as Fc/BW (central freq/bandwidth ). What does Q mean for a low pass filter. 2)Is it just the 2nd order filters which have Q or even 1st order, 3rd order, higher order systems have a Q factor. Can someone also post a link for a good refence on...
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