what are the reasons behind set up and hold time??

[natish.singla89]

I know what is set up and hold time. My question is what are the reasons behind this set up and hold time.
Waiting for reply

 

[kumar_eee]

Reasons behind the setup & hold time!!!... I dont understand what exactly you're looking for.

Can you elaborate more on your doubt?

 

[srizbf]

the minimum time you must allow for the parasitics to charge
to the specified voltage.

srizbf
24thjune2010

 

[kumar_eee]

If you dont satisfy the setup & hold requirements, the output of the flop will be unpredictable. It is called metastable state.

 

[gmajay123]

1) Flipflop is back to back latches. for a +ve edge triggered flipflop you have a negative latch followed by positive latch.
2) Latch when implemented physically with transistors has some propagation delay.
3) In this case setup time is the propagation delay of negative latch. So when the positive latch is being enabled ( at the +ve edge ) you want to have the o/p of your negative latch to be stable.

 

[nsingh95]

I know what is set up and hold time. My question is what are the reasons behind this set up and hold time.
Waiting for reply

Hi ,
All these setup , hold specifications are maintained as per the Flop manufacturing contraints.Take a hard ware point of view.Whenever a data comes as an input to the flop, the flop takes a snapshot of the input data .The time at what the flop takes the snapshot depends on the flop implementation.So, the data must not change after it takes the snapshot because the flop internal logic could not determine which input to implement and it goes to metastability.
Hope u understand....

 

[supercat]

I know what is set up and hold time. My question is what are the reasons behind this set up and hold time.

Nearly all latching circuits, at the most basic level, can be reduced to some combination of combinatorial circuitry and one or more set-reset latches. When the
"set" input of the latch is active and "reset" is inactive, everything in the latch will be forced into a known state. Likewise when the "reset" input is active and "set" is inactive, everything will be forced into a different known state. When neither input is active, and everything in the latch is in one of the two good states, the latch will keep its present state.

If every pulse on "set" or "reset" is long enough that everything within the latch achieves its proper state, the latch will behave as expected. If, however, a "runt" pulse arrives on the "set" or "reset" input, however, things can go wonky. For example, if the latch had been cleanly reset and an overly-brief pulse arrives on "set", some of the circuitry may be knocked out of the "reset" state, but not all of it put in the "set" state, before the input pulse goes away. At that point, since the latch's circuitry as a whole won't be in either of the two "legitimate" states, there's no particular guarantee as to what the latch will do. States other than the two legitimate ones are called "metastable".

The output of the latch may cleanly switch from low to high as expected. The output of the latch may also simply sit low, as though there weren't any pulse at all. Ideally, the latch would always do one of those two things. Unfortunately, life isn't ideal.

The output of the latch could output a brief high pulse before returning low. It could also oscillate a few times before ending up either high or low. It could also stay low until after the input had gone away, and then switch high a little later, or it could switch high, stay high for awhile, and then go back low.

Note that it is possible to design latching hardware to rule out specific bad behaviors, but one can't rule them all out. Indeed, attempting to rule out one bad behavior will generally cause some other bad behavior to become more likely. There are also techniques to reduce the probability of bad behaviors, but many such techniques will limit the maximum speed of a system.

The essential thing to note is that while the most probable effect of setup/hold violations will be that the system may grab either old data or new data, it's entirely possible that an input which changes within the setup/hold interval may cause the output to switch in weird and wacky ways that don't correspond with a high or low input.

A common solution to such behavior when using flip flops is to feed the output of one latch into another. While it would be possible for the output of the first flip flop to decide to switch just as the next flip flop was about to be clocked, in practice it would be very unlikely that the first flip flop would fall out of its metastable state at just the right moment to jinx the second one. Theoretically, it could happen, but the probability would generally be infinitesimal.

 

[alaparthi]

1) Flipflop is back to back latches. for a +ve edge triggered flipflop you have a negative latch followed by positive latch.
2) Latch when implemented physically with transistors has some propagation delay.
3) In this case setup time is the propagation delay of negative latch. So when the positive latch is being enabled ( at the +ve edge ) you want to have the o/p of your negative latch to be stable.

The above explanation is the right way to look at it.
For basic flip flop circuit implementation, please refer to:
**broken link removed**

For ppt version:
**broken link removed**

 

[itsmeteja]

All the cmos flipflops are designed with the combo logic followed by a 2phase clock transmission gates, this two phase clock controls the gate inputs of the tx/.. gate. This dependency has brought the setup and hold concept..

If both the transmission gates are ON/OFF at the same time wrong data will be captured. Which is called Race problem or metastability. This problem has been safely removed in the NORA circuits, but they have their own disadvantages.