Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi, Microchip has a relatively new MCU family called the PIC32MZ. These processors are for embedded purposes but also have an MMU for virtual memory support. Has anyone used the MMU on this processor? I don't have a particular problem I'm working on that deals with this, just curious as to who...
The design rules from the foundry should come with guidelines on pad<->core spacing for SI, xtalk and other electrical reasons. Saying what exactly you're violating or what exactly will go wrong if your core area is too close to your IO area is tough to say. Is your design DRC clean?
The net area is answered in posted #6. The total area is the standard cell area and the macro/memory area. The net area and the total area units are defined by the tool.
What synthesis tool are you using?
Net area is defined by the tech library you're using, the # of interconnections, the metal layers used for routing, and the wire lengths. But pre place & route, this is not a useful figure I would imagine.
All of them? Like leaf cells vs hierarchical cells? A hierarchical cell is a cell made up of leaf cells and possibly other hierarchical cells. A leaf cell on the other hand doesn't instantiate any other instances. When the netlist is flattened, hierarchical cells no longer exist. Does that help...
Yes, incremental delays from the nets and the cells are explained in the timing report for the path with the -nets option for PrimeTime's report_timing.
I don't know what synthesis tool you're using and I'm actually not looking at any synthesis tool manuals at the moment but I'll try to answer some of these.
1. The net area is probably a figure relating to the amount of routing resources used. I'm guessing this defined in the technology section...
When you add net information to timing reports (like -nets for PrimeTime's report_timing command for example), the net delay information is added to the same table as the cell delay information.
Engineers can use this information to find out if their path delays are wire dominated or cell dominated.
I don't think the IO pad design for flip chips is much different than wire bond chips. The IO pad functionality is still needed like heavenevil says. The flip chip IO pads are even arranged similarly around the die compared to non-flip chip designs. A redistribution layer (RDL) is created to...
I have not used back-end tools for logic synthesis. In my experience that would be an unusual design flow and I'm not aware of any back-end tools that do that. At the pre-ECO stage, front end designers synthesize the logic and hand off the netlists to the physical design team. This is probably...
I'm not sure what the best power analysis "point" tool is but I can say that switching back and forth between different design tools working on different views is quite common in IC design. There just is no push button flow.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
