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I did that. I have compiled through my Xilinx Suite the libraries a dozen times. But i still get this error.
library unisim not found.
if i run the project through modelsim. question: do i have to do this for every project?
If I run for example the post synthesis model generated in xilinx ise in modelsim stand alone, it asks for the unisim library to be imported? Where do I find it? In the modelsim folder or in the xilinx? in which path?
I am in modelsim and choose File->Import->Library but then I do not know...
thats the same link as the one I posted. Well this is the error I get.
udo file already exist (landmark.udo). It will not be re-generated.
* creating main do file (landmark.fdo) for Behavioral Simulation...
> executing 'C:/Modeltech_pe_edu_10.0d/win32pe_edu/vsim.exe -version' to get the...
If i run modelsim separately it runs without a problem. i just cannot start it inside xilinx. any other links on how to do it? Maybe I am missing a thing.
Hello. I am trying to simulate from xilinx using modelsim. I have used this tutorial **broken link removed**and I have also included in my path system variable the path of modelsim ("c:\modelsim_version\win32" folder). But then I try to run the simulation and I get this: it says running...
Well this is my testbech code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.my_package.all;
entity tb_landmark is
generic
(N :integer := 8;
NA:integer:=3);
port (
rst: in std_logic;
vin: in...
Well as this is my first synthesis, I need your help so as to realize certain things and be able to continue my project. I am using a Virtex6 , and my ISE is that ot Xilinx.
My code is this:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use...
Re: Warning in Synthesis
Ok some newbie questions about the above.
Ok to begin with, lets consider the code above. Why it will work only for some period of time? Sorry for the foolish question maybe, but i have just started to work on such a project.
so you mean in the reset section, giving...
ok here is another warning I get. Is it serious?
Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim landmark.ngc landmark_synthesis.v
WARNING:NetListWriters:677 - Netgen has detected a port, dout<0>[23], at
instance, landmark, that is declared as...
I am getting this warning for almost every signal that I use:
Xst:737 - Found 1-bit latch for signal <line_finished>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
can anyone...
This was my initial code:
storing: for k in 0 to 10 loop
inside: for l in 0 to 10 loop
sum_of_square_all(k)(l)<=signed(ext(sum_of_square(inp1(k),inp2(l),"000000000000000000000000"),3*N));
wait for 15 ns;
end loop inside...
In order not to open a new thread can anyone help me on this: what if i want to pass as an argument a whole single row of a 2d array. I am calling my function something like this but i get error . This is my code:
match(k)<=find_min(k,0 to 3);
I want to avoid using a for loop. Is there any way...
Next on this: If I add this code after the reading of my arrays:
storing: for k in 0 to 3 loop
inside: for l in 0 to 3 loop
sum_of_square_all(k,l)<=signed(ext(sum_of_square(inp1(k),inp2(l),"000000000000000000000000"),3*N));
end loop inside;
end loop storing...
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