ghostridergr
Member level 1
Well this is my testbech code:
the flag doesn't seem to take a value (to tell the truth I do not see it in the wave). My flag signal is an std_logic and when is H, my vhd does the final computation and gives me the dout signal. if I run it manually it run normally. By running the testbench, i see all the signal taking their values and my dout remains UUUU. The problem seems to be that the value of the falg "doesn't pass" in the my real vhdl to make it find the dout.
and this is my code:
thanks for your help.
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.my_package.all;
entity tb_landmark is
generic
(N :integer := 8;
NA:integer:=3);
port (
rst: in std_logic;
vin: in std_logic
);
end tb_landmark;
architecture TB_ARCHITECTURE of tb_landmark is
file IN_1_VECTORS: TEXT open READ_MODE is "input_1.txt";
file IN_2_VECTORS: TEXT open READ_MODE is "input_2.txt";
file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";
component landmark
-- generic (N :integer := 8;
--NA:integer:=3);
port ( clk:in std_logic;
new_set: in std_logic;
vin:in std_logic;
din: in signed(N-1 downto 0);
rst: in std_logic;
dout: out big_matrix(0 to 3);
done: out std_logic
);
end component;
--here
--type matrix1_t is array(integer range<>) of signed(N-1 downto 0);
--type big_matrix is array(integer range<>) of signed(3*N-1 downto 0);
--type matrix2d is array (integer range<>) of big_matrix(0 to 3);
signal clk:std_logic;
signal new_set: std_logic:='0';
signal a,b: signed(N-1 downto 0):= (others=>'0');
signal flag:std_logic:='0';
signal dout:big_matrix(0 to 3);
signal done: std_logic;
signal din:signed(N-1 downto 0);
begin
UUT: landmark
port map (
clk=>clk,
new_set=>new_set,
rst=>rst,
vin=>vin,
din=>din,
dout=>dout,
done=>done,
flag=>flag);
process
variable IN_BUF: LINE;
variable OUT_BUF: LINE;
variable a_var,b_var : bit_vector(N-1 downto 0):= (others=>'0');
variable i,j: integer;
-- variable c_var,d_var : bit_vector(N-1 downto 0):= (others=>'0');
--variable sum_var:std_logic_vector(3*N-1 downto 0):= (others=>'0');
begin
i:=0;
j:=0;
while not ENDFILE(IN_1_VECTORS) loop
new_set<='0';
READLINE(IN_1_VECTORS,IN_BUF);
READ(IN_BUF,a_var);
din<=signed(to_stdlogicvector(a_var));
wait for 50 ns;
i:=i+1;
end loop;
new_set<='1';
while not ENDFILE(IN_2_VECTORS) loop
-- new_set<='1';
READLINE(IN_2_VECTORS,IN_BUF);
READ(IN_BUF,b_var);
din<=signed(to_stdlogicvector(b_var));
wait for 50 ns;
j:=j+1;
end loop;
flag<='1';
wait for 1 ms;
for q in 0 to NA loop
WRITE(OUT_BUF,to_bitvector(std_logic_vector(dout(q))));
WRITELINE(OUT_VECTORS,OUT_BUF);
end loop;
done<='1';
wait;
end process;
process
begin
clk<='0';
wait for 50 ns;
clk<='1';
wait for 50 ns;
end process;
end TB_ARCHITECTURE;the flag doesn't seem to take a value (to tell the truth I do not see it in the wave). My flag signal is an std_logic and when is H, my vhd does the final computation and gives me the dout signal. if I run it manually it run normally. By running the testbench, i see all the signal taking their values and my dout remains UUUU. The problem seems to be that the value of the falg "doesn't pass" in the my real vhdl to make it find the dout.
and this is my code:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.my_package.all;
entity landmark is
generic
(N :integer := 8;
NA:integer:=3 );
port ( clk:in std_logic;
new_set: in std_logic;
vin:in std_logic;
rst:in std_logic;
din: in signed(N-1 downto 0);
dout: out big_matrix(0 to 3);
done: out std_logic;
help: out signed (23 downto 0)
);
end landmark;
architecture TB_ARCHITECTURE of landmark is
signal inp1,inp2: matrix1_t(0 to NA);
signal flag:std_logic:='0';
signal k:integer range 0 to 100:= 0;
signal l:integer range 0 to 100:= 0;
signal i:integer range 0 to 100:= 0;
signal j:integer range 0 to 100:= 0;
signal sum_of_square_all: matrix2d(0 to NA);
signal min: signed (23 downto 0):="000000000000000000000000";
function sum_of_square_dif( a1,b1: in signed(N-1 downto 0); previous_sum:in std_logic_vector(3*N-1 downto 0))return std_logic_vector is
variable temp_sum:std_logic_vector(3*N-1 downto 0):=(others=>'0');
variable diff: signed(N-1 downto 0):=(others=>'0');
variable square_diff: std_logic_vector(2*N-1 downto 0):=(others=>'0');
begin
temp_sum:=previous_sum;
diff:=a1-b1;
square_diff:=ext(diff*diff,2*N);
temp_sum:=ext(temp_sum+square_diff,3*N);
return temp_sum;
end sum_of_square_dif;
begin
in_read: process (clk,rst)
begin
if (rst='1') then
--mhdenise mnhmh
elsif (clk'event and clk='0') then --reading at negative edges.
if (vin='1') then --vin enable signal
if (new_set='0') then
if (i<=NA) then
inp1(i)<=din;
i<=i+1;
end if;
else
if (j<=NA) then
inp2(j)<=din;
j<=j+1;
end if;
end if;
if ((j>NA)and(i>NA)) then
flag<='1';
end if;
end if;
end if;
end process in_read;
f_min: process(clk)
variable temp_num: signed (23 downto 0);
begin
if (clk'event and clk='1') then
if (flag='1') then --finished reading
if (k<=NA) then
temp_num:=signed(ext(sum_of_square_dif(inp1(k),inp2(l),"000000000000000000000000"),3*N));
help<=temp_num; --be removed
done<='0';
if(l<NA) then
if (l=0) then
min<=temp_num;
elsif (temp_num< min) then
min<= temp_num;
else
min<=min;
end if;
l<=l+1;
else --last element of each row
if (temp_num< min) then
dout(k)<= temp_num;
else
dout(k)<=min;
end if;
l<=0;
k<=k+1;
min<=signed(ext("0",3*N));
end if;
else
done<='1';
end if;
end if; --end of if flag='1'
end if;--end of clk'event
end process f_min;
end TB_ARCHITECTURE;thanks for your help.