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Recent content by GhostInABox

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    Availability of small RAM in ASIC cell library

    Hi all, I have been out of ASIC design for sometime now. Just want to check if using a cell library would the cell library also provide the ability to initialize small RAM modules ? , Say 128 byes or so. I am wondering if this is going to be SRAM based with simple access interface, could you...
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    Fixed point Math for FFT, DSP in FPGA

    I have a working understanding of it. There were a lot of questions which is difficult to reiterate here but it goes to the heart of fixed point math implementation.
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    Fixed point Math for FFT, DSP in FPGA

    Hi all, I have done quite a bit of searching on the net and a bit of VHDL coding to model and learn how to use fixed point numbers . I understand the basic concepts ( or do I ? ) . But at a recent interview got my ass handed to me by the interviewer , so i am thinking that i really need to...
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    VHDL editor, synthesis tool and simulator for FPGA's

    Hi all, I realised that my approach to HDL development is very inefficient. I am still uncertain on how some of the constructs will be synthesized and have to go back and forth between the Synthesis tool ( VIVADO ) . But waiting for VIVADO or ISE to synthesise my design each time is painful. I...
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    Xilinx ROM inference not working using VHDL

    @ads-ee Well I dont think a ROM is suitable in this specific problem, and I understood that after realizing that it was a clocked element that would not give me 4 coefficient values at the same time. I have done ASIC in the past so i thought coefficent(0) <= to_signed(10,8); would give...
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    Xilinx ROM inference not working using VHDL

    @ads-ee i am learning fast that inferring blocks that you want is painful :(... I spend a bunch of time trying to infer a ROM @FvM and you are right in pointing out why it wont infer, i dont know what i was thinking when i wrote that piece of code, i totally forgot that a ROM element can only...
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    Xilinx Coding Style for Synthesis and ieee package usage

    Hi All , I noticed that most of the coding templates in the vivado user guide and most of the templates available in VIVADO itself use ieee.std_logic_arith , which is the synopsys package. I know that it should not be mixed with ieee.numeric_std ( in the same file) So I was wondering if...
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    Xilinx ROM inference not working using VHDL

    I have the following VHDL implementation of a 4-tap FIR filter , I have looked at the VIVADO user guide on ROM generation , while the code from the user guide works i dont see any ROM's generated in my design when i used it. 1. I dont know if it makes sense but i am defining a ROM that has...
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    Xilnx ISE RTL schematic Viewer and FPGA Design Flow

    Thanks FvM... Well it was VERY confusing for me to see what i saw in ISE because I am still not that confident with my VHDL and I was not sure if i had coded up my solution correctly. After synthesis schematic is mainly LUT's and FF's so its hard to see how my code has interpreted. I also try...
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    Xilnx ISE RTL schematic Viewer and FPGA Design Flow

    @ads-ee thanks for your comments if you look at my VHDL , I have a coefficient port but in the RTL schematic viewer(ISE) , i dont see that port. Also if you look into the structure of the synthesized HW, the ISE image shows that internal signals are grounded when they are not , it should show...
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    Xilnx ISE RTL schematic Viewer and FPGA Design Flow

    Hi all , I am modelling the following code in ISE(12.4) and VIVADO , VIVADO(2014) elaborated schematic seems to give quite accurate results while i am struggling to see how ISE RTL schematic viewer is useful to the RTL designer at all ? Here is the code for a FIR filter with 4 taps library...
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    fixed point multiply accumulate in VHDL for Xilnx FPGA

    Hmm... , i was not talking about floating points ( at least i dont think so ) . in my sample code, as you mentioned i was just assigning fixed point values. whatever the value we assign what i understood is that the package makes sure that it fits in the range by rounding. What i noticed is...
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    fixed point multiply accumulate in VHDL for Xilnx FPGA

    @TrickyDicky @linam , thank you both for your input I was on my way to draw a block diagram on how it should look when i came across this excelent link https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/ @linam I looked at that link i did not understand why floating point numbers...
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    fixed point multiply accumulate in VHDL for Xilnx FPGA

    Hi All, I need to implement a tapped FIR filter in a Xilinx FPGA using VHDL . This means that i will need to do fixed point multiplication and addition. I have read through some of the post on the xilinx and edaforum and not closer to understanding the best way to represent fixed point numbers...
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    DSP math interview questions and fundermentals

    Hi All, I have a 2 questions 1. What are the most critical maths you need to know when going for a DSP + FPGA interview ? , e.g multiplying 2 N bit numbers will take up 2* N bits. 2. How many bits are needed for a MAC unit ( say you have two 16 bits inputs to a multiplier which goes in the a...
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