GhostInABox
Junior Member level 2
I have the following VHDL implementation of a 4-tap FIR filter , I have looked at the VIVADO user guide on ROM generation , while the code from the user guide works i dont see any ROM's generated in my design when i used it.
1. I dont know if it makes sense but i am defining a ROM that has singed values , this makes it easy for me to specify values in decimal form,
2. I would like to load the coefficients from the ROM
3. Do i have to have the ROM in a seperate module for the inference to work
Thanks in advance
1. I dont know if it makes sense but i am defining a ROM that has singed values , this makes it easy for me to specify values in decimal form,
2. I would like to load the coefficients from the ROM
3. Do i have to have the ROM in a seperate module for the inference to work
Thanks in advance
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package temp is
type tapType is array (integer range <>) of signed(7 downto 0);
end package temp;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.temp.all;
entity FIR_SLOW2 is
port( clk : in std_logic;
en : in std_logic;
reset : in std_logic;
input : in signed(7 downto 0);
output : out signed(7 downto 0));
end FIR_SLOW2;
architecture Behavioral of FIR_SLOW2 is
signal tap : tapType(3 downto 0);
signal coefficent : tapType(3 downto 0);
type tapType_internal is array (integer range <>) of signed(15 downto 0);
signal tap_internal : tapType_internal(3 downto 0);
signal add3 : signed(17 downto 0);
signal data : signed(7 downto 0 );
signal addr : std_logic_vector(3 downto 0);
type rom_type is array (3 downto 0) of signed (7 downto 0);
signal ROM : rom_type:= (to_signed(2,8),to_signed(2,8),to_signed(2,8),to_signed(2,8));
ATTRIBUTE rom_style : STRING;
ATTRIBUTE rom_style OF ROM : SIGNAL IS "BLOCK";
signal data1 : signed(7 downto 0 );
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
data <= ROM(to_integer(unsigned(addr)));
end if;
end if;
end process;
coefficent(0) <= ROM(0);--to_signed(8,8);
coefficent(1) <= ROM(1);--to_signed(10,8);
coefficent(2) <= ROM(2);--to_signed(4,8);
coefficent(3) <= ROM(3);--to_signed(6,8);
tap_proc:process(reset,clk)
begin
if(reset = '1') then
for i in 0 to 3 loop
tap(i) <= to_signed(0,8);
end loop;
output <= to_signed(0,8);
elsif(rising_edge(clk)) then
for i in 3 downto 1 loop
tap(i) <= tap(i-1);
end loop;
tap(0) <= input;
output <= add3(17 downto 10);
end if;
end process;
process(tap,coefficent)
begin
for i in 0 to 3 loop
tap_internal(i) <= tap(i) * coefficent(i);
end loop;
end process;
process(tap,tap_internal)
variable add1 : signed(16 downto 0);
variable add2 : signed(16 downto 0);
begin
add1 := resize(tap_internal(0),17) + resize(tap_internal(1),17);
add2 := resize(tap_internal(2),17) + resize(tap_internal(3),17);
add3 <= resize(add1,18) + resize(add2,18);
end process;
end Behavioral;