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Recent content by ghegde

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    Verification techniques for FPGA prototyping.

    Thanks TrickyDicky for the reply. The actual Design Under Test(DUT) will be a router for NoC(Network on Chip). The design is not yet ready but I am just thinking about the verification techniques in advance. Thanks Ganesh
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    Verification techniques for FPGA prototyping.

    Hello, I am in the phase of designing and implementing a digital circuit for a FPGA.I wonder how a digital circuit logic(described in HDL) is verified before synthesizing to a FPGA.I used to write test bench for simple digital circuit before but the design at hand is now complex and writing...
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    [SOLVED] AMS .35um:Calibre DRC problems

    I don't think the contacts/well ratio was the problem, because in one of the trial I put many contacts(in almost all free space ) in the nwell,but i still had that problem.
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    Help needed to understand the pre and post layout simulation results.

    Thanks Nitishn5 for the reply. I am newbie in this field,so can you please help me to know, what are the different technique usually followed to identify the leakage in layout?Any reference to book or weblink will be useful. Thanks :)
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    Help needed to understand the pre and post layout simulation results.

    Hello, I have designed a Clock buffer(Inverter chain buffer). Here are my pre(schematic ) and post layout simulation data, Parameter Pre Post Static current 14.79pA 57.31pA Peak current 7.99mA 7.03mA Avg. current 0.671mA...
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    Spectre_simulator : Post layout verification problem

    Sarge,Thanks for the reply. I am using Mentor Graphics Calibre as PEX.
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    Spectre_simulator : Post layout verification problem

    Hello, I am facing a problem while doing a post layout simulation of a simple inverter chain.I ran a transient analysis on current through voltage supply node(minus terminal) with an intention to know the current flowing through the circuit at different instant of time. Below is my Test...
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    [SOLVED] AMS .35um:Calibre DRC problems

    Found a solution!!!! Instead of using one big nwell,I split it into 3 small nwell.That made the error to vanish. I still wonder how this resolved the error?How one big nwell was hot but not the small chunks which added together will yield the same area.Note that there is no change in Ntap...
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    [SOLVED] AMS .35um:Calibre DRC problems

    Hi, Thanks for the reply.I placed the nwell contact such that they are not more than 25um apart.But it didn't resolve the problem :(
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    [SOLVED] AMS .35um:Calibre DRC problems

    Hello there, I have DRC error which says nwell is hot,though the nwell is connected to vdd!. I am not able to understand why I am getting this error. Any help regarding this is greatly appreciated. I have attached the layout screen shot for your reference. Thanks in advance,
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    [SOLVED] AMS design rules(0.35um) : Understadning "Geometric relation"

    Thank you all for your help :)
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    [SOLVED] AMS design rules(0.35um) : Understadning "Geometric relation"

    Thanks erikl for the reply :) I am just curious to know which scenario causes this.Whether Metal1 and Metal2 overlap(without a via in between) is an example?
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    [SOLVED] AMS design rules(0.35um) : Understadning "Geometric relation"

    Hi, I have trouble in understanding "Geometric relations" section in AMS design rules document.It is mentioned for example like 'A extension of B EnAB := distance inside_A - outside_B (A may intersect B)' what is 'distance inside_A' and 'outside_B' ???? and how it should be interpreted...
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    [SOLVED] Which is good Cyclone IV(Altera) or Sparten-3E (Xilinx)

    Thanks a lot for your suggestion :) I was comparing between https://papilio.cc/ and https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593.DE0-Nano is better right? Thanks and regards ghegde
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    [SOLVED] Which is good Cyclone IV(Altera) or Sparten-3E (Xilinx)

    Hi I need to buy a new FPGA board.Which board is good to buy?one with Cyclone IV(Altera) or Sparten-3E (Xilinx)? Thanks in advance ghegde
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