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Recent content by gauz

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    how fpga(spartn6) caputres data in such a interface?

    Hi all, In my design there is a TI transcever tlk2211 interfaces to spartn6, which send data(RD) in ddr mode, and sourced with two inverted clk(RBC0/1) to capture the data in each of the rising edge. the waveform as shown in the attachment, I'm a little puzzled how should I capture the...
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    Help! xilinx routing fail caused by BUFGMUX

    Should I lock the BUFGMUX in ucf file? how could I know which BUFGMUX isn't confilicted? without map ncd file, I have difficult to open fpga editor. Regards, Gauz
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    Help! xilinx routing fail caused by BUFGMUX

    Hi, It run into error when mapping my spartn6 based design, the error info as below, ERROR:Place:1023 - Unroutable Placement! A global clock component <userapp_inst/bufgce_inlp> configured as a selectable mux is placed in site BUFGMUX_X2Y1. This configuration requires that the global...
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    MCB generated by CoreGenerator simulation fails!

    Hi, I run the MCB simulation with all the files generated by core generator, the simulation could run up, but report DATA ERROR and stopped after some time later, what maybe the problem? I use ISE12.4, modelsim6.5se, target spartn6, and run the simulation at windows command line mode...
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    lvcmos33 io maping fails while lvcmose 25 pass(ise8) why???

    error:pack:1654 Thanks for Pootle's reply. I slacked the clock frequency but the same error occurs. I leave the io location no specified and the io standard is still lvcmos33, it pass too. it's really a puzzling bug, no more hint from ise tool but the "ERROR:Pack:1654 - The timing-driven...
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    lvcmos33 io maping fails while lvcmose 25 pass(ise8) why???

    lvcmos25 lvcmos33 group:comp.arch.fpga I implement a design in spartn3, and set the io standard to lvcoms33(or lvttl) but it always fails in mapping "ERROR:Pack:1655, the timing-driven phase encoutered an error". if I change the io standard to lvcmos25, then it pass. Dose anybody know what's...
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    setup time is less than hold time,will this cause problem???

    Hi all, below is part of the twr file, we can see that the setup time is much less than the hold time, this means the input clock delay is much greater than the input data delay, will this case any potential problem? the interface is a standard pci interface and connected to pci board...
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    How could I do ECO in fpga implementation!!!

    thank! I use par.ncd file as the guide file and guide mode is set to leverage for both map and par, but it seems still timing consuming, no the feel of speed-up.
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    How could I do ECO in fpga implementation!!!

    I had a large design, and it's really time consuming to run the full flow through from synthesis to map to par, if I had run the flow for one time, and then I found some pads constraints need to be re-allocated, how could I got the new implement quickly, just as run ECO in asic design??? Must...
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    how could I fix hold violations in my design &#65311;&am

    Re: how could I fix hold violations in my design &#65311 here are two violations, it tells the clock skew is larger than data delay. BTW, all effort are set highest. ================================================================================ Timing constraint: TS_fpga_clk_gen_inst_clk_hsx...
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    how could I fix hold violations in my design &#65311;&am

    There is large clock skew introduced by DCM in my design, so the .twr always report hold violations. but I think it should'nt by a big trouble for ISE, only insert some delay cell and the violations could be fixed, why ISE couldn't do it automaticly when P&Ring? does anyone know how to fix it?
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    why more clock skew when use DCM rather than no DCM?

    thanks for you answer. I do buffered the DCM output clock by primitive 'BUFG'. I'll take a look at the FPGA editor tomorrow.
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    why more clock skew when use DCM rather than no DCM?

    Hi, all there are several clock in my design, here is two case for comparison: 1, Input only one clock,'clk_in', and all other clocks are derived from this input clock by DCMs, specify only the input clock period, the design report HOLD time violation. 2, Input all clocks from external ...
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    what maybe the cause of a diff freq betw. CLKIN and CLK0???

    I implement a test code in virtex4, to my surprise, the CLK0 is different from the effective CLKIN, DCM_BASE is generated with all setting default .CLKIN 50MHz while clk_int 5MHz and LOCKED is active. What maybe the causes? (rst_dcm_n is internal pullup) the main code below: CLK_HAPS,rst_dcm_n...
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    why timing simu fails while post PAR rpts no timing errors??

    Hi, Everyone I implemented my design in xilinx spartn3, PAR is ok, no timing violation reports after STA, but when I run timing simulation with the simulaltion file generated by ISE, the X_FF(which is a cell in lib simprims_ver) report setup and hold violation. I am puzzled and don't know...
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