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Help! xilinx routing fail caused by BUFGMUX

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gauz

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Hi,

It run into error when mapping my spartn6 based design, the error info as below,

ERROR:place:1023 - Unroutable Placement! A global clock component <userapp_inst/bufgce_inlp> configured as a selectable

mux is placed in site BUFGMUX_X2Y1. This configuration requires that the global clock site BUFGMUX_X2Y2 either be

empty or contain a global buffer or mux with the inputs IN0 and IN1 either not driven by a signal or driven by the

same signals as the original muxes IN1 and IN0 pins respectively in order to route up both of the inputs. In other

words the input signal for IN0 on one buffer must be the same as the input signal driving IN1 on the other buffer (or

one of them must not be driven) to place the two buffers in the paired sites. The site BUFGMUX_X2Y2 has the global

buffer <userapp_inst/app_pcie_inst/PIO_EP/regs_module_inst/mux_msgwrclk> placed there. This design is unroutable.
ERROR:pack:1654 - The timing-driven placement phase encountered an error.

Does anyone has any suggestion on this?

Thanks in advance,
Gauz
 

You can lock your BUFGMUX to be on a certain position which does not cause any conflict, or you can add an area constraint to avoid the conflict, I think.
 

You can lock your BUFGMUX to be on a certain position which does not cause any conflict, or you can add an area constraint to avoid the conflict, I think.

Should I lock the BUFGMUX in ucf file? how could I know which BUFGMUX isn't confilicted?
without map ncd file, I have difficult to open fpga editor.

Regards,
Gauz
 

Yes, you can lock it in the ucf file. I don't know which device you are using, but there are number of accessible BUFGs from a pin. Why don't you select one which is not near your differential signal input?
 

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