Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
500 mhz dac
In 90nm CMOS, to design a 6-8 bit, 500MHz DAC, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative DACs. Any thoughts on this? Thanks.
Re: How does buffer (or amplifier) affect Oscillator's jitte
The jitter can be expressed in terms of the noise at the output and the slope of the output voltage at zero crossing. Refer to the paper "Phase noise in digital frequency dividers" published in JSSC May 2004
cadence noise summary
In the Results Display Window of noise summary in Cadence Spectre simulation, there is a list like the following:
Device Param noise distribution % of total
/M0 id 1e-7 40
/M0 fn 2e-8 8
I want to...
Hi Nimer,
Thanks for your comments. Where does the 25mV thermal noise come from? The signal I'm talking about is from on-chip circuit, not from the wireless communication. The bandwidth of A(t) is as small as 1KHz. So actually the integrated noise is not that much.
Added after 58 minutes...
I want to detect the envelope(amplitude) of a signal V(t)= A(t)cos(2pi*f*t), where f=200Mhz and A(t) is a low-frequency signal (almost dc). The range of A(t) is about 1mV to 10mV. Is there any paper or book talking about such circuit? Thanks.
How can a band-pass filter with fcenter=200MHz implemented on chip? The spec of the bpf is loose: bandwidth: 100MHz; gain can be less than 0dB; on-chip inductor is not available. Any suggestions? Thanks a lot.
frequency dependant inductor model
The inductance is a function of frequency. How can I model this for simulation? I checked Hspice, Verilog-A. There's no such function.
I'm simulating the 1dB compression voltage of an amplifier. It's weird that the gain is not monotonically decreasing when the amplitude of input signal increases. For instance, from 25mV to 150mV, the gain increases from 1.55 to 1.63. Then from 150mV to 300mV, it decreases from 1.63 to 1.33...
In my chip, there is a 200-MHz input signal with an amplitude of 400mV. It's connected to the gate of an NMOS transistor. Is it OK to directly connect the signal pad with the transistor gate? Is it necessary to put some buffer? What kind of buffer would be appropriate? Thanks.
I want to know the typical jitter performance of a 100MHz crystal resonator. I searched some crystal resonators. But only the frequency stability info is available in the spec. What's the typical rms jitter of a 100MHz crystal resonator?
When we design the passive devices, such as inductor, transformer, S parameters of the devices can be simulated by electromagnetic simulation software, such as HFSS or Sonnet. Then the parameters of the equivalent circuit model can be derived by some software, such as HSPICE. But sometimes...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
