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Hi,
the prerequisite is ordinary differential equation (ODE)
I'm not sure what do you mean by geometric interpretation but this book might be helpful
books.google.com/books?isbn=0470458364
Hi,
I want to add an action to state diagram in active-hdl so that the action be executed with every pulse, how can I do that?
I mean the code must be somthing like this:
...
elsif (clk' event and clk = '1') then
-- the action that runs with every rising clk edge
case state -- state...
hi,
I get this warning:
Xst:1336 - (*) More than 100% of Device resources are used
and this is my device utilization summary:
why this warning appears?
hi,
this is my code
OUTDATA : PROCESS(sSELECT,sDATA1,sDATA2,sDATA3,sDATA4,sDATA5,sDATA6)
BEGIN
if (sSELECT = "000") then
pDATAOUT <= sDATA1;
elsif (sSELECT = "001") then
pDATAOUT <= sDATA2;
elsif (sSELECT = "010") then
pDATAOUT <= sDATA3;
elsif (sSELECT = "011") then
pDATAOUT...
Hi,
I want an article form the website of kyushu university, which has been blocked for me recently. It was open to anyone weeks ago.
Is there anyone from kyushu university in this forum who can please help me?
Hi,
I want to know the price of OLED lighting products; like this one:
winona trilia - canvis
https://www.winonalighting.com/products/new_products/oled_custom/tri_-_straight
I don't want to personally contact them and ask for price; however I don't know if they will answer me and give me the...
Hi,
I want to extract the PID from a TS
this is the code that I'm proposed to use
...
ID(7 downto 0) <= DATA_IN;
ID(15 downto 8) <= ID(7 downto 0);
DATA_OUT <= ID(15 downto 8);
...
PID <= ID(12 downto 0);
this is the TS header:
I think if I use this VHDL code, by...
You are very wise! :lol: Considering my internet connection speed which is a 256Kbps (shared with 5 other users) and costs 6$ per mounth and considering that the ISE is about 4GB, it takes almost 35 hours for me to download it, of course if the connection does not lose. Thank you for your very...
Hi,
when I try to simulate a code which has a fifo core in it I get this error:
ERROR:HDLCompiler:104 --- Cannot find <fifo_generator_v4_2> in library <xilinxcorelib>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
WARNING:sim -...
yes it exists.
yes I know, actually I deleted some part of the code because I thought those parts might cause the problem; this code is the simplest one which just reads the contents of a file; if I be able to successfully read the contents of a file, then I would put them in RAMB and after...
Hi,
here is my testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
library std;
use std.textio.all;
-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS
END test_tb...
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