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Hi Guys,
I'm working with an LCD that has AVDD (5V power) and DISP (3.3V logic) lines. The datasheet says that DISP should not go high before AVDD. Therefore I'm planning to switch them both with a pair of logic-level MOSFET's. Will this layout work do you think? The idea is that the 1K gate...
Yes, that's correct. I'm not sure I was completely clear, or even slightly clear, but I have SPI flash for loading the FPGA configuration at bootstrap and a second flash device for data storage use at runtime. I'll be programming both of these in-circuit.
That sounds like a good strategy. I...
Hi,
I have a question about the power-off state of the I/O ports on the Spartan-3.
My FPGA design communicates with an SPI flash IC and I'd like that flash IC to be in-circuit programmable by an MCU so I have broken out the SPI communication pins to a header for that purpose.
During flash...
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