Power-off state of Spartan 3 I/O ports

[foxbat_gb]

Hi,

I have a question about the power-off state of the I/O ports on the Spartan-3.

My FPGA design communicates with an SPI flash IC and I'd like that flash IC to be in-circuit programmable by an MCU so I have broken out the SPI communication pins to a header for that purpose.

During flash programming by the MCU the power to the FPGA will be disconnected, but what will the state of the ports be? I'm particularly concerned about the SCLK and MOSI pins that the MCU will drive for programming. If the FPGA has these connected to ground when power is off then I'll have a short circuit which is obviously bad.

I'm looking forward to hearing your advice.

Regards,
- Andy

 

[ads-ee]

foxbat_gb,

If the FPGA is powered down (i.e. no power applied to the Vcc pins) then the I/O cells will have no power and they won't be shorted to ground if that is your concern. My concern would be applying a voltage to the un-powered pins of the FPGA and and potentially supplying some power to the I/O ring of the FPGA through the substrate. These types of scenarios tend to be not so good for the device.

It looks like your running the Spartan-3 in a master SPI serial configuration mode and want to be able to program the flash using the MCU. You should be able to power the FPGA, but hold off configuration with the MCU by driving the configuration (might be INIT, but I'm too lazy to check the S3 docs) pin low on the FPGA. I believe (besides holding off configuration) this will keep the FPGA from driving SCLK and MOSI.

Regards

 

[foxbat_gb]

foxbat_gb,
It looks like your running the Spartan-3 in a master SPI serial configuration mode and want to be able to program the flash using the MCU.

Yes, that's correct. I'm not sure I was completely clear, or even slightly clear, but I have SPI flash for loading the FPGA configuration at bootstrap and a second flash device for data storage use at runtime. I'll be programming both of these in-circuit.

foxbat_gb,
You should be able to power the FPGA, but hold off configuration with the MCU by driving the configuration (might be INIT, but I'm too lazy to check the S3 docs) pin low on the FPGA. I believe (besides holding off configuration) this will keep the FPGA from driving SCLK and MOSI.

That sounds like a good strategy. I remember reading somewhere either in the S3 datasheet or the very large configuration guide appnote that the IOs are in high impedence until configuration is complete.

Regards,
- Andy

 

[mrflibble]

I remember reading somewhere either in the S3 datasheet or the very large configuration guide appnote that the IOs are in high impedence until configuration is complete.

I vaguely recall the exact same thing for spartan-3.

 

[ads-ee]

Well the user I/O will be in a high impedance state throughout configuration. The question is whether or not the MOSI and SCLK will be in hi-Z if you keep the PROGRAM or INIT pin low. I believe it does, but I would verify that is the case.

https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
See pg 111 of the UG332 (v1.6) October 26, 2009 and it shows that PROG_B will Hi-Z all the IO including the PROM configuration pins so you can directly access them.

regards