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most design rule violations can be fixed in the backend. but your violations can be a indication with the quality of your synthesis, such as dont_touch_network is creeping into your datapaths.
clock drivers have better slew, drive capability, and higher power consumption. A clock buffer will usually have better balance with rise and fall time.
Best to check your datasheet.
synthesis is pretty reliable now, unless your coding style is really poor.
chances are your gate level simulation setup is not correct, it may be either reset or time step related.
Reg: Physical Design
80% is pushing it. If you want to reduce the density by 5%, then most likely it would require changes in design architecture. Neither synthesis nor floorplanning can reduce the density by that much, unless the implementation is drastically wrong.
Reg: Hold time
1.. data path, but you have to minimize clock skew in the backend.
2. hold time problem will show up on reg to reg on a very sort data path, due to clock skew.
3. minimize your clock skew, review your clock uncertainty specification. *analyze* your timing report, not just...
Test Coverage
code, or line, coverage is old school. The draw back is it could hide untested variables, i.e. an OR condition.
For functional coverage, google specman, coverage groups, metric, table, etc.
One place to start is to look at set_case_analysis in your synthesis scripts, which give...
agreesor.net
i can answer a few of your questions:
:: how to see the untested path in PT... it means false path ?
in encounter, which sounds like you have, do "report_timing -unconstrained
:: what we will see in glitch analysis and noise analysis report?
encounter will perform clock gating...
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