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below are my code for haar block...
as u can see from the pic waveform above, there only 8 input and 8 output. the error i got is "input already exist" event i wrote in0[7..0].................in63[7..0]... im expecting to have 64 input and 64 output.
LIBRARY ieee;
USE...
sory i dont get it..
i want 64 input and output..but there on 8 input and output even i wrote in0[7..0].................in63[7..0]
and same for the output..
i got this code.. but there is error .. its said to "....many to fit in 385 availbale.." maybe because of the loop problem.. i dont have any idea to fix it.
2nd is how to make output from below code to feed above code?
package newtype is
type row_t is array(0 to 3) of integer;
type matrix_t is...
hi..
i have problem
1. on how to design input for matrices to insert to my coding (1D) then
2. code for transpose module of the matrices
sory i have problem in attach the file ..so i copy my code below :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY haar IS
PORT
(...
hi.. anyone help me..
what is the suitable input and output that should i write? because i got unwanted input and output in waveform simulation like in the 4th pic..
i mean the simulation doesnt show any error.. but the output is not what i want..
for ie :
c<= (a-b)/d
the output should be -1 if
variable d : integer := 2;
variable a : integer := 5;
variable b : integer := 7;
but in simulation it shows 1. it should be -1
and if i change :
variable d ...
no.. because i run this code in quartus version 8.1
there is no error in the simulation
hmm
sory.. i send wrong code.. this is the actual one
sory.. this is the correct one...
LIBRARY ieee;
USE ieee.All;
ENTITY beza IS
PORT (
clk : IN bit;
c : OUT integer RANGE -127 TO 127
);
END beza...
LIBRARY ieee;
USE ieee.All;
ENTITY beza IS
PORT (
clk : IN bit;
c : OUT integer RANGE -127 TO 127
);
END beza;
ARCHITECTURE beza OF beza IS
BEGIN
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk='1'THEN
variable d : integer := 2;
variable a : integer := 5;
variable b : integer := 7;
c<=(a-b) / d;
END...
hai, im newbie....any idea for this..?
ARCHITECTURE beza OF beza IS
BEGIN
PROCESS (clk)
variable d : integer := 2;
variable a : integer := 5;
variable b : integer := 7;
BEGIN
IF clk'EVENT AND clk='1'THEN
c<=(a-b) / d;
the output should be -1.. but i got 1.
and if i change variable a into 3...
im newbie..
here are my code for division.. but its still error..
hope someone may give some idea
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY purata IS
PORT
(
a:IN integer RANGE -127 TO 127;
b:IN integer RANGE -127 TO...
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