unwanted output vhdl waveform

[Farid Ishak]

hi.. anyone help me..
what is the suitable input and output that should i write? because i got unwanted input and output in waveform simulation like in the 4th pic..

 

[mrflibble]

The very first line in this post is the first step towards your solution: https://www.edaboard.com/threads/314682/#post1345620

 

[Farid Ishak]

sory i dont get it..

i want 64 input and output..but there on 8 input and output even i wrote in0[7..0].................in63[7..0]
and same for the output..

 

[TrickyDicky]

You really are not describing the problem well. What inputs and outputs are you refering to? the Haar block? or the top level? Where is the code for the HAAR block?

You need to be much more specific. All we have is a top level diagram with some blocks unconnected and some random waveform.

 

[Farid Ishak]

below are my code for haar block...
as u can see from the pic waveform above, there only 8 input and 8 output. the error i got is "input already exist" event i wrote in0[7..0].................in63[7..0]... im expecting to have 64 input and 64 output.




LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY haar IS
PORT
(
clk : IN STD_LOGIC;
in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in7 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
out0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out5 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out6 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
out7 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END haar;

ARCHITECTURE bdf_type OF haar IS

COMPONENT daftar
PORT(clk : IN STD_LOGIC;
i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

COMPONENT purata
PORT(clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

COMPONENT beza
PORT(clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_39 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_46 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_47 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_48 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC_VECTOR(7 DOWNTO 0);


BEGIN



b2v_inst : daftar
PORT MAP(clk => clk,
i => in0,
o => SYNTHESIZED_WIRE_36);


b2v_inst1 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_36,
b => SYNTHESIZED_WIRE_37,
c => SYNTHESIZED_WIRE_42);


b2v_inst10 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_38,
b => SYNTHESIZED_WIRE_39,
c => SYNTHESIZED_WIRE_46);


b2v_inst11 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_40,
b => SYNTHESIZED_WIRE_41,
c => SYNTHESIZED_WIRE_47);


b2v_inst12 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_42,
b => SYNTHESIZED_WIRE_43,
c => SYNTHESIZED_WIRE_48);


b2v_inst13 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_36,
b => SYNTHESIZED_WIRE_37,
c => SYNTHESIZED_WIRE_30);


b2v_inst14 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_44,
b => SYNTHESIZED_WIRE_45,
c => SYNTHESIZED_WIRE_31);


b2v_inst15 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_38,
b => SYNTHESIZED_WIRE_39,
c => SYNTHESIZED_WIRE_32);


b2v_inst16 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_40,
b => SYNTHESIZED_WIRE_41,
c => SYNTHESIZED_WIRE_33);


b2v_inst17 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_46,
b => SYNTHESIZED_WIRE_47,
c => SYNTHESIZED_WIRE_49);


b2v_inst18 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_48,
b => SYNTHESIZED_WIRE_49,
c => SYNTHESIZED_WIRE_26);


b2v_inst19 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_42,
b => SYNTHESIZED_WIRE_43,
c => SYNTHESIZED_WIRE_28);


b2v_inst2 : daftar
PORT MAP(clk => clk,
i => in1,
o => SYNTHESIZED_WIRE_37);


b2v_inst20 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_46,
b => SYNTHESIZED_WIRE_47,
c => SYNTHESIZED_WIRE_29);


b2v_inst22 : beza
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_48,
b => SYNTHESIZED_WIRE_49,
c => SYNTHESIZED_WIRE_27);


b2v_inst23 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_26,
o => out0);


b2v_inst24 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_27,
o => out1);


b2v_inst25 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_28,
o => out2);


b2v_inst26 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_29,
o => out3);


b2v_inst27 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_30,
o => out4);


b2v_inst28 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_31,
o => out5);


b2v_inst29 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_32,
o => out6);


b2v_inst3 : daftar
PORT MAP(clk => clk,
i => in2,
o => SYNTHESIZED_WIRE_44);


b2v_inst30 : daftar
PORT MAP(clk => clk,
i => SYNTHESIZED_WIRE_33,
o => out7);


b2v_inst4 : daftar
PORT MAP(clk => clk,
i => in3,
o => SYNTHESIZED_WIRE_45);


b2v_inst5 : daftar
PORT MAP(clk => clk,
i => in4,
o => SYNTHESIZED_WIRE_38);


b2v_inst6 : daftar
PORT MAP(clk => clk,
i => in5,
o => SYNTHESIZED_WIRE_39);


b2v_inst7 : daftar
PORT MAP(clk => clk,
i => in6,
o => SYNTHESIZED_WIRE_40);


b2v_inst8 : daftar
PORT MAP(clk => clk,
i => in7,
o => SYNTHESIZED_WIRE_41);


b2v_inst9 : purata
PORT MAP(clk => clk,
a => SYNTHESIZED_WIRE_44,
b => SYNTHESIZED_WIRE_45,
c => SYNTHESIZED_WIRE_43);


END bdf_type;

 

[TrickyDicky]

Please post the project..