Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I need small help regarding the floating gate device. I am designing a non-volatile memory cell and foundry does not have model for floating gate . So I used the Voltage controlled current source to mimic floating gate. For output characteristics, I already had the measurement of...
Thank you for ur help. Yes the logic is XNOR, but XNOR has 2 inputs , while I have 1 data input and other is just the enable to invert the data or not. In the 2nd logic , by latch I mean I want to keep the state output state constant depending on the input logic. E1 and E2 are Enable 1 and 2...
2-state Buffer with enable
Hello,
I have a question that is there any circuit that only inverts the o/p signal when enable is high other wise it should behave as a normal buffer.
The truth table is
E = Enable
A = Input
X = Output
E A X
0 0 0
0 1 1
1 0 1
1 1 0
The output is Enable dependent...
Hey, Thank for your help!
The problem was with the mirror ratio of tail current source, I used the ratio of 1 instead of 2. I have simulated this design by fixing the common mode DC voltage and sweeping differential voltage from -0.3V to +3V and tail current is approx 2.2 uA (1.1 uA for each...
Thanks, I have one more confusion, I tried to simulate the top design (shown in main post schematic), but the gain is very low. I noticed that the DC operating points seems to be incorrect.
I have setup the schematic and test bench shown in images. The problem is the upper PMOS sources VDS is...
Hey, Thank you for the explanation. if I am not wrong then by DC reference voltage source you mean to attach a voltage source after the inductor and the DC source voltage has the same value as the drain voltage at differential pair transistor ?
Hello,
I am simulating differential pair with current mirror and current source (attached image , top is with current source and bottom with current mirror configuration) and I have confusion regarding operating point. I am following Electronics circuits book by tietze and schenk and there it...
Thanks for your help.
In equations the first part requires values that are not directly known, I need to analysi to calculate V_out,
in 2nd part,Δgm=gm1-gm2, Rd = load resistor , Rss is current source resistance. do you know any better equation to calculate common mode gain with resistive and...
Hello,
I am simulating differential pair with resistive load and another with active load with differential output, I have read onlone and razavi book that Active load improves CMRR and also differential gain, but reason for this is not mentioned. can anyone guide me why we replace load...
Thanks everyone, the problem was the operating points, in regular cascodes, Trasistors were operating at different operating points than wide swing configuration. Now the output resistance is almost same.
Hello,
I have a small confusion regarding the Output resisitance of Cacode current mirror and Wide wing cascode current mirror. As per my knowledge, both of these have same output resistance. But when I calculated thru AC simulation its giving me different values for resistance.
Kindly see the...
Hello,
I am testing a MOSFET differential pair with resisitive load and as well as Active (MOS) loads. In DC simulation with resistors as load I can calculate the Differential Output voltages and Currents but with MOS loads I also want to calculate the differential output (vout1 vout2) which...
Hey ppl,
I have started learning SKILL by my self and I have three questions regarding my project.
I converted symbol in to schematic (Layout XL: connectivity->Generate->copy all from source). The layout has instance of pcell which is nfet without nwell. I wanted to place nwell somwhere near...
Hello All,
I want to measure the Output voltage for 5-6 different combinations for the DAC.
Inputs are I0 I1 I2 I3 I4 I5 and Outputs are O0 O1 O2.
Example Inputs
111000
110011
101101
101010
I have tesbench in spectre language I just want to sneek in and use spice commands after selecting...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
